The threshold voltage (V_th) is a crucial indicator in determining the health of the gate of a power semiconductor. In response to the challenges posed by low measurement accuracy and a lack of standardization in SiC MOSFET V_th test, a design scheme for a high-precision measurement circuit for SiC MOSFET V_th based on the JEP183A standard is proposed in this paper. Firstly, an initial analysis was conducted on the JEP183A requirements for the V_th sampling circuit, identifying the functional modules and components for the circuit implementation. Secondly, Then the operational principle of each functional module of the V_th sampling circuit is described. Finally, the testing of three sets of SiC MOSFET devices from the same batch verified the proposed circuit. Experimental results demonstrate V_th repeatability error below 4.7% with absolute accuracy of ±0.01 V under 3 V drain-source bias conditions. This paper contributes to the first reproducible hardware implementation of the JEP183A standard, thus providing an effective test tool for V_th measurements.

We present a study using epoxy adhesive to directly couple perovskite single crystals to Topmetal CMOS pixel charge sensors. Topmetal-II^- is a low-noise integrated pixel sensor with a 72×72 pixel array of 83.2 µm pitch, capable of directly collecting external charge through exposed metal electrodes in the topmost metal layer. The proposed coupling layer is formed by mixing pure epoxy resin and hardener in different proportions, which exhibits both good electrical and mechanical strength to perovskite single crystals due to its tunable resistivity ranging from 1×10⁸Ω cm to 5×10¹²Ω cm, long-term stability, and strong bonding strength. We successfully bonded Topmetal-II^- sensors to two types of perovskite single crystals to form hybrid device prototypes using this method and demonstrated its potential applications for high-spatial-resolution imaging, particularly in X-ray imaging.

This paper analyzes the common-mode interference conducted by the planar transformer in an isolated DC-DC converter and proposes a scheme for common-mode interference suppression. The scheme integrates the compensation capacitor for suppressing the common-mode current into the planar transformer, and its working principle is briefly explained in the paper. In addition, the scheme is verified by an active clamped forward converter. The application of this scheme in forward converter requires that the filter inductor on the secondary side be placed between the source of MOSFETs and the ground of secondary side, and it is necessary to add an inductor at the feedback terminal of the compensation loop, which needs to be coupled with the secondary filter inductor to ensure the normal driving of the MOSFETs. Finally, we made a prototype with an input voltage of 28 V and an output voltage of 5 V, and tested the common-mode interference of the prototype when using different planar transformers, which verified the feasibility of the scheme proposed in this paper.

Gate oxide degradation plays a critical role in the reliability of SiC MOSFETs. This paper proposes a method for predicting SiC MOSFET gate degradation based on on-state resistance variation (ΔR_ON). ΔR_ON, which is induced by gate voltage changes, strongly correlates with gate degradation. The relationship between ΔR_ON and gate degradation is derived through theoretical analysis and validated through testing at different temperatures. During prediction, a gate drive circuit induces gate voltage transients, and both I_DS and V_DS before and after the transients are measured to calculate ΔR_ON. An iterative method is used to find the solution that best matches the calibrated relationship. Experimental results demonstrate the method’s effectiveness in accurately predicting gate degradation across various temperatures and degradation levels.

Switched reluctance motor (SRM) with ring winding structures exhibits significant current and torque ripple due to their nonlinear electromagnetic characteristics. To address this issue, this paper proposes an adaptive fractional-order PI^λD (FOPI^λD) controller with a parameter tuning method that dynamically adjusts control parameters based on DC voltage, nonlinear inductance, and delay time. A Simulink-based simulation of a single-phase inductive circuit verifies the feasibility of the proposed method. The adaptive FOPI^λD controller is further applied to an SRM control system, with simulation and experimental results demonstrating its effectiveness. Compared to the traditional hysteresis current controller, the proposed approach significantly reduces current and torque ripple across different operating conditions.

This letter presents a integer-N quadrature oversampling phase-locked loop (QOPLL) operating at 5.76-6.48 GHz with low RMS jitter. The QOPLL features a calibration-free gain-boosting quadrature oversampling mechanism. The proposed gain-boosting quadrature oversampling mechanism addresses the incompatibility issues in conventional oversampling mechanisms and gain-boosting techniques. It enhances in-band phase noise performance while eliminating the need for phase detector gain calibration. An isolated reference sampling phase detector (IRSPD) has been developed to ensure quadrature phase accuracy and improve phase detector gain. The QOPLL is fabricated in a 40-nm CMOS process. Measurement results demonstrate an RMS jitter of 103 fs, integrated from 10 kHz to 100 MHz. The reference spur is -71.26 dBc. The power consumption is 15 mW.

Mismatched circuit components in analog-to-digital converters (ADCs) caused by imperfect fabrication processes significantly degrade the ADC performance, and there have been various attempts to address this by carrying out on-chip ADC calibration. However, calibration accuracy suffers from the defects of on-chip circuitry (called design-for-calibration (DfC) circuits) designed to facilitate those calibration processes, which are introduced by variations in the manufacturing process.

Unfortunately, it is hard to calibrate on-chip DfC circuit itself on a device-by-device basis, because of low controllability and observability for on-chip circuits. This paper proposes an efficient built-off self-calibration methodology to externally calibrate ADCs on the proposed load board, by making a detour around the nonlinear portion of a code-width (CW) based on the differential-nonlinearity (DNL), thereby improving ADC linearity. This work migrates the required DfC circuitry to an external load board as well as bare dies wherever possible, in order to eliminate even the possibility of the degradation by on-chip DfC circuits. For simplicity, it is assumed that the mid-code of an ADC has a CW that is wider than a least-significant-bit (LSB) voltage, i.e., wide CW to be calibrated only. The key idea of this work is as follows: the transfer function (TF) for the ADC can be split into two halves, i.e., an upper TF and a lower TF to calibrate the mid-code. If an input signal falls in the upper TF, then it is shifted up by half of the remaining width at the mid-code, excluding one LSB voltage. Similarly, if an input signal falls in the lower TF, then it is shifted down by half of the remaining width. As a result, any input signal can bypass the remaining width at the mid-code, excluding one LSB voltage, so that the TF can be linearized. This process can be realized using the proposed load board configured with an analog adder, a comparator, a binary-weighted capacitor array called level shifter, and a simple digital logic called level logic including a computation logic and a switch logic. To evaluate the performance of the proposed work, a 12-b 40-MSPS split-capacitive digital-to-analog converter successive-approximation ADC under calibration and the proposed circuitry with 8-bit capacitor array were separately designed in 0.18-µm CMOS. Simulations based on this work verified that the proposed methodology can be practically used, by showing that the total-harmonic-distortion was enhanced from 71-dB to 81-dB.

Nonlinear dynamical systems such as biological systems require substantial resources for digital circuit implementation due to their nonlinearity. This study approximates these systems by converting to the quantized-state system (QSS) solved using the forward Euler method and efficiently implements them on a field-programmable gate array (FPGA). Focusing on coupled nonlinear oscillators that mimic neural circuits, we evaluate the benefits and limitations of the QSS in terms of hardware resource usage and accuracy compared to the original system solved using the forward Euler method. The results provide valuable insights for the miniaturization and energy efficiency of neuromorphic hardware.

With the increasing demand for health monitoring and biometric identification technologies, radar-based heartbeat signal extraction techniques have been widely applied and deeply researched. This article proposes a time-domain method for heartbeat signal extraction, employing a cubic spline-based heartbeat enhancement algorithm combined with an adaptive bandpass filter. The proposed method offers significant advantages, including a simplified computational process and reduced time delay compared to conventional signal decomposition techniques, making it highly suitable for real-time applications. Additionally, it provides higher confidence and better interpretability than signal extraction methods based on neural networks. To achieve this, the method enhances the heartbeat signal of the continuous-wave (CW) radar output signal using cubic spline curve interpolation. The heartbeat signal is subsequently extracted by dynamically adjusting the frequency range of a bandpass filter. The method is implemented on a 2.4 GHz CW radar system based on a phase discriminator, which features a simpler structure and higher accuracy compared to traditional quadrature receivers. Experimental results in multiple subjects validate the effectiveness of the proposed approach, demonstrating an average heartbeat count accuracy of up to 98.06% in the time domain compared to the reference signal collected by the wearable sensor. Furthermore, the method achieves a computational complexity of O(N), highlighting its efficiency and potential for practical deployment.

IGBT module requires accurately intermediate layer temperatures (ILT) monitoring to ensure system safety and reliability. Considering critical failure factor of solder layer voids, this paper implements real-time monitoring to IGBT module ILT using DT. By deriving the nonlinear relationship between thermal resistance of solder layer and junction temperature, a mathematical model is refined to more precisely reflect the actual thermal behavior of IGBT. A nonlinear intermediate layer temperatures observer is designed to further improve the accuracy. Experimental validation demonstrates that, the proposed observer significantly enhances the precision with an error of only 0.1% compared to traditional methods.

A novel parameter extraction method for the Schottky diode’s equivalent-circuit model is proposed, and used to design high-efficiency microwave rectifier circuits. This method only use the Vector Network Analyzer (VNA) to extract the nonlinear intrinsic parameters and linear parasitic parameters in the equivalent circuit through the S-parameters of Schottky diode ports measured under different bias voltages. Taking the Schottky diode HSMS270B as an example, the parameters are extracted and modeled by this method, and it is verified that the simulation results are strongly correlated with the measured results in a microwave rectifier circuit with the operating frequency of 2.45 GHz, particularly in terms of the relationship between the output voltage of the rectifier circuit and the input power.

To explore and quantify the performance of data features for classifying the state of the scale layer of the homogeneous electrode by ultrasonic detection, this paper proposes a data robustness test method. The method takes the ultrasonic detection signal of homogeneous electrode as the research object, firstly obtains the frequency band of the reflection signal of homogeneous electrode in the ultrasonic signal with the appetite signal for the characterisation, and proposes the confidence ellipsoid robustness test of the scale layer, and proves the reasonableness of the data feature extraction in the article, which provides a certain value of engineering for the field of ultrasonic detection.

This paper presents a 6 bits 10 MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) utilizing a multi-conversion dynamic amplifier (MC-DA) to enhance power efficiency. The MC-DA enables voltage-time conversion on both rising and falling clock edges, reducing clock frequency and dynamic power consumption. A shoot-through prevention (STP) latch ensures accurate conversions, while a reset generator accelerates reset times, improving throughput. A dual-ring counter-based clock generator optimizes phase alignment. Measurement results from a 0.5 μm CMOS implementation show a signal-to-noise and distortion ratio (SNDR) of 34.52 dB and a spurious-free dynamic range (SFDR) of 43.08 dB. The proposed ADC achieves significant power savings, making it suitable for low-power applications.

The conventional FCS-MPC operates by selecting a switching state per control cycle through cost function optimization. However, it is possible for this method to consistently select the same switching state, resulting in high THD and switching frequency variability. This paper proposes a modified FCS-MPC with fixed switching frequency for voltage source inverters (VSIs) based on conditional suboptimal switching. When the optimal vector matches the previous one, the vector that sub-optimizes the cost function is selected. Simultaneously, a duty cycle modulation scheme applies to this suboptimal state via time-modulated actuation. The proposed strategy reduces THD while fix the switching frequency. Hardware experiments are conducted to verify the effectiveness of the proposed strategy.

Audio noise suppression techniques are commonly utilized across diverse audio systems,often relying on general-purpose processors. However, this leads to inefficiencies in terms of hardware resource usage, energy consumption, and overall system expense. This paper presents a specialized microcontroller for audio noise suppression,based on the Hummingbird E203 framework. Key hardware optimizations include enhanced multiplication and division units using Booth4 encoding, Wallace tree, and dual SRT-4 mechanisms, alongside the integration of an F instruction set for floating-point operations. A camouflage strategy reduces memory transaction complexity. Software improvements utilize adaptive spectral subtraction for efficient noise suppression. Benchmarks show a 4002.5% boost in floating-point performance and significant gains in noise reduction, with a 54.6% decrease in noise energy and a 28.7% rise in signal-to-noise ratio, highlighting its efficacy.

Superconducting computers can be realized using a Josephson-CMOS hybrid structure, combining the high speed and low power of single-flux quantum (SFQ) logic with the high integration density of CMOS technology. However, reliable interconnection between SFQ and CMOS circuits at cryogenic temperatures remains challenging due to low signal-to-noise ratio (SNR) and interference. To address these challenges, we propose a DC-biased SiGe BiCMOS interface that converts the 0.2 mV output of the SFQ/DC converter (Q2D) to 1.2 V for CMOS memory. A high-impedance voltage amplifier (VA) and a low-impedance transimpedance amplifier (TIA) were designed to optimize signal matching with the Q2D. The interfaces were simulated, fabricated, and tested at 4.2 K to evaluate their performance. Both analytical and experimental results demonstrate that the TIA significantly improves the SNR and enhances noise immunity during static random-access memory (SRAM) read/write operations, making it more effective than the VA for signal matching between the Q2D and CMOS circuits. This work presents a practcal solution for SFQ-CMOS interconnection, effectively addressing SNR and interference challenges and contributing to the development of scalable superconducting computing systems.

With the widespread use of analogue circuits, current reference (CR) trimming has become an increasingly important issue. Therefore, finding a reliable and area-efficient trimming method becomes more and more critical. In this paper, a novel area-efficient memristor-based trimming circuit for current reference (CR) with temperature coefficient optimization capability is proposed. The proposed trimming core circuit uses only the source-degraded current mirror embedded in the memristors, thus achieving a significant area reduction.The circuit produces an output of approximately 5.2 μA, and test results show a calibrated output temperature coefficient (TC) of less than 75 ppm/°C over the temperature range of -20°C to 120°C, with a linearity of 4.3% /V over 2.2 to 4 V. The circuit implementation uses 0.18-μm CMOS technology. The layout area is less than 0.0016 mm², representing average area savings of 84.3% over the current state of the art in trimming circuits.

In low-voltage servo systems powered by batteries, as the battery continues to discharge and the system enters an under-voltage condition, the PMSM's torque becomes limited due to the saturation of back electromotive force during motor startup. Additionally, in steady-state operation, the output torque is constrained. To address these issues, a novel control strategy is proposed that combines the Quasi-Z-source network with the low-voltage servo drive. The rate of change of the phase current amplitude of the PMSM is introduced as a compensation factor into the voltage loop control of the Quasi-Z-source network. This approach enhances the DC bus voltage and its dynamic response performance, thereby improving the motor's output torque. Consequently, the proposed strategy effectively improves the system's response speed and output capability under battery under-voltage conditions.

This paper proposes a directory-based hierarchical cache coherence protocol for highly scalable Chiplet architectures. The proposed protocol can be seamlessly divided into two independent levels, the first level handling the inter-core cache coherency within a single Die while the second level dealing with the intra-Die cache coherency across multiple Dies. The proposed protocol is implemented using a two-level directory structure which exhibits superior scalability in terms of storage overhead. Simulation results indicate our approach using a two-level directory structure reduces the miss rate of the shared last-level cache (LLC) as compared to conventional approach using a single-level directory structure. This reduction enhances overall cache performance as the average memory access latency is reduced.

Logic locking is a technique designed to safeguard integrated circuit netlists from security threats. However, recent advancements in machine learning-based structural attacks have significantly challenged existing logic locking methods. Moreover, current defenses against these structural attacks often diminish the resilience of logic locking against Boolean satisfiability-based attacks (SAT attacks). To address this limitation, this paper presents the Depth-Coupling Logic Locking (DCLL) technique. DCLL utilizes a key to control a multiplexer and an XOR gate, establishing a robust interconnection at the functional level. By incorporating subgraph replacement, DCLL enhances both the locking mechanism and its resistance to SAT attacks. Experimental results reveal that DCLL achieves an exponential increase in SAT attack resistance while maintaining robustness against machine learning-based removal attacks. Furthermore, DCLL provides a balanced defense against oracle-guided (OG) and oracle-less (OL) attacks. For circuits with one million gates, DCLL incurs minimal overheads of 0.37% in area and 0.40% in power, positioning it as an efficient and effective solution for enhancing the security of logic locking techniques.

Detecting hardware Trojans (HTs) in mixed-signal circuits is challenging due to structural complexity and cross-domain vulnerabilities between analog and digital components. Existing methods often rely on post-silicon analysis, circuit modifications, or focus solely on leakage, limiting practicality. We propose HGAT4TJ, a pre-silicon detection approach based on heterogeneous graph attention networks, which models gate- and transistor-level structures in a unified graph. This enables effective cross-domain HT detection directly from netlists without requiring golden models. Experimental results on benchmark circuits indicate that HGAT4TJ achieves 100% detection rate at the circuit level and over 97% accuracy at the node level, making it a non-invasive solution for HT detection in mixed-signal circuits.

Digital cancellation is a key method for interference suppression in communication systems but it fails under receiver saturation. This paper proposes a novel signal folding-based interference cancellation architecture to prevent signal clipping caused by dynamic range overflow. We then combine the folding method with stochastic logic to reduce hardware costs, addressing the bottleneck of traditional stochastic computation where adders, rather than multipliers, limit performance. A new stochastic adder enables signal folding in the probability domain, which facilitates efficient interference suppression. Measurement results demonstrate that the proposed design reduces delay by at least 52.4% and lowers hardware costs by 59.6% compared to conventional approaches.

This letter presents a C-Ku-band high-efficiency power amplifier (PA) fabricated using 0.25µm gallium nitride (GaN) high electron mobility transistor (HEMT) technology. A novel bias network criterion, which quantifies the bandwidth-efficiency tradeoff and is used to improve the high-band efficiency, is thoroughly discussed. The partial harmonic control amplification cell (PHCAC) design method is applied to obtain the optimum source and load impedances for each transistor in the PA’s output stage at both fundamental and second harmonic frequencies, thereby enhancing the mid-band efficiency. In addition, the intrinsic PAE of the transistor is sufficiently high at low frequencies, resulting in a higher overall efficiency. The proposed 7-13 GHz high-efficiency GaN PA MMIC delivers an average output power of 42.1-43.3 dBm (16.2-21.3 W) with a power-added efficiency (PAE) of 38%-43% and a gain of 30.7-32.9 dB under a drain voltage of 28 V. The proposed GaN PA MMIC occupies an area of 13.1mm²

This paper proposes a background digital calibration technique for high-speed multi-channel time-interleaved ADCs (TI-ADCs) to address sub-channel memory nonlinearities and inter-channel mismatch errors. The method employs a simplified DDR-based Volterra series model with reduced parameters. An improved Input-Free Band (IFB) error detection scheme eliminates the need for reference channels or test signals, ensuring uninterrupted ADC operation. To effectively overcome non-convex optimization challenges, the proposed approach employs a customized artificial bee colony (ABC) algorithm to extract Volterra kernel coefficients. Validated through simulations and a 1-Gsps 14-bit 2-channel PI-SAR ADC prototype, the technique demonstrates effective compensation for subchannel memory nonlinearities and inter-channel first-order mismatches, achieving SFDR improvements of 11.67-24.69 dB across input frequencies. The fully-digital solution offers versatility and portability for diverse ADC architectures.

A 16-bit 210MSPS pipelined analog-to-digital converter (ADC) with distributed differential reference voltage buffer (DDRVB) and for-ground calibration is presented. Current summing and floating current control techniques are used in DDRVB to achieve high precision adjustable reference voltage. In order to improve the power supply rejection ratio (PSRR) and reduce the output impedance and power consumption, the push pull output and replica circuit structure is introduced. A mix-signal for-ground calibration method for pipelined ADC is proposed. Offset, gain and mismatch errors in pipelined sub-stage circuits can be compensated by the proposed calibration method. Based on the proposed DDRVB and calibration method, a prototype 16-bit 210MS/s pipelined ADC is designed and realized in a 1P6M 0.18μm CMOS process. Test results show, the 16-bit 210MSPS ADC core achieves the signal-to-noise ratio (SNR) of 77.3dB and spurious free dynamic range (SFDR) of 101.7dB, with 5.1MHz input at full sampling speed, while consumes the power consumption of 495mW.

For neural network accelerators with General Matrix Multiplication (GEMM) as the computational core, the input feature maps of convolution must be converted into 2D matrices through the Im2col operation. Conventional approaches utilize CPUs to execute Im2col management and data transfer operations. Conventional methods suffer from memory expansion due to redundant data in overlapping convolutional windows, thus incurring non-negligible memory access energy consumption and transmission latency overheads. This severely limits the feasibility of efficient GEMM acceleration in resource-constrained edge devices. This paper proposes a novel Low Memory Access Im2col Method (LMAI2C) and present its dedicated hardware implementation. By restructuring data from overlapping convolutional windows, LMAI2C significantly reduces DRAM memory access volume while improving feature map transfer efficiency. Experimental results on convolutional layers of the YOLOv4-tiny network demonstrate that LMAI2C reduces DDR memory access by approximately 79.8% compared to traditional methods. Furthermore, LMAI2C demonstrates an average speedup of 69 times compared to CPU-based methodologies and 43 times over DMA-accelerated CPU implementations.

We propose a novel device for sub-terahertz (sub-THz) signal generation via optical difference frequency generation (DFG). The device features a T-branch waveguide with two components: a LiTaO₃ crystal-embedded main waveguide for sub-THz signal generation and a sapphire (Al₂O₃) dielectric waveguide side branch that acts as a coupler. In the experiment, a 100 GHz signal is successfully generated, and the T-branch configuration efficiently separates the lightwaves from the generated signal, facilitating integration into advanced sub-THz applications. The measured frequency response of the proposed device is in very good agreement with the calculated results.

This paper presents a high-speed single channel reconfigurable successive approximation register (SAR) analog-to-digital converter (ADC) for ultra-high-speed system. The ADC operates in two modes: 1GS/s 8-bit and 1.5GS/s 6-bit. A floating-skip algorithm is proposed to address the speed limitation and amplitude attenuation of input signals in 6-bit operating mode, while avoiding unnecessary switching power consumption. Meanwhile, the ADC employs binary redundant CDAC to improves the fault tolerance range and relaxes the requirements for setting accuracy, further achieving high conversion speed. The reconfigurable ADC is designed in the 28-nm CMOS process, it achieves the 36.69-/47.68-dB signal-to-noise-and-distortion ratio (SNDR) at 1-/1.5-GHz sampling rate with the same power consumption of 4.42 mW. The ADC core occupies an active area of only 0.003948 mm². It achieves a FoMw of 22.31 fJ/conv.-step at 8-bit conversion mode.

CLLC converters are widely used in bidirectional DC applications, particularly in aviation and vehicle power supplies, requiring high dynamic commutation performance. This paper presents a commutation control method for CLLC converters based on a state trajectory model. The forward and reverse state trajectory models are developed, and the optimal commutation trajectory is derived. The gate drive signal's pulse width is calculated based on the post-commutation gain. Simulations validate the proposed model's accuracy and the control method's dynamic performance, showing significant improvement over traditional linear control methods.

A fully tunable bandpass filter based on convex resonators is proposed in this letter. Independent tuning of the center frequency and bandwidth of the filter is achieved by adjusting the tunable capacitors loaded at different positions on the resonator. This tunable filter has the advantages of large design freedom, wide adjustment range, and easy cascading to improve the out of band suppression performance. To verify the proposed idea, a 3-order fully tunable bandpass filter was designed and fabricated. The measured results show that the center frequency of the fully tunable filter can be tuned in the range of 223MHz-537MHz, with a frequency variation range of 82.6%, and a 3dB bandwidth tunable in the range of 54MHz-73MHz.

Self-feedback test vector generation uses the circuit itself to generate test vectors, which greatly reduces the cost of testing without relying on other equipment. However, there are a great number of feedback nodes in the circuit, so how to select the feedback scheme is a problem. This paper proposes an adaptive matching method to select the self-feedback scheme. First, the final feedback nodes are selected by using the self-defined test vector similarity in the adaptive matching method, and then the optimal arrangement order of feedback nodes is determined by using the self-defined test vector matching degree. The self-feedback structure of the sequential circuit is improved and the number of multiplexers (MUXs) is reduced. The test vector similarity and the test vector matching degree are introduced into the parameters TR and Cr of the Spider Wasp Optimization Algorithm (SWO), respectively, so that the parameters can be adaptively adjusted in the process of selecting feedback nodes.

This article presents a 100 Gb/s four-level pulse amplitude modulation (PAM4) analog front-end (AFE) implemented in TSMC’s 28-nm CMOS process. The continuous-time linear equalizer (CTLE) employs the transconductance (GM) stage for mid-frequency (MF) peaking, while leveraging the transimpedance (TIA) stage to produce high-frequency (HF) peaking. This allows the HF peak frequency to remain constant as the boost range is adjusted. While the variable gain amplifier (VGA) employs shunt inductive peaking and feedforward technique to extend bandwidth. Both CTLE and VGA use complementary structures to improve linearity. Frequency response tests show the AFE has a 31 GHz peak frequency and a 33.1 dB gain boost. Eye diagram measurements confirm it can open eyes for 100 Gb/s PAM4 signals.

Cost aggregation is a crucial step in the accurate stereo depth estimation process known as semi-global matching. However, this step is challenged by storing large amounts of aggregated data, which is necessary to achieve high matching accuracy under large resolution and large disparity conditions. In this paper, we propose a multi-path optimization aggregation strategy and re-select the complementary combinations of key paths in the forward and backward scanning directions to improve the matching accuracy as much as possible. An error rate of only 5.21% is achieved on the KITTI 2015 dataset. Next, we propose DCT-based truncated compression and selective storage to alleviate the problem of memory increase due to the introduction of reverse critical aggregation paths. Experiments show that the matching error rate increases by only 0.6% on the KITTI 2015 dataset with 53% memory savings. Finally, 1920 × 1080 @62fps @128MHz is achieved on ZCU102 FPGA.

This paper proposes a novel topology of grain-oriented electrical steel permanent magnet synchronous motor (GO-PMSM) with spliced teeth-yoke structure for electric vehicles, aiming to address the vibration challenges under high power density demands. Two motors (GO-PMSM and NO-PMSM) with identical dimensions were designed. Through theoretical analysis and multiphysics finite element modeling, the magnetostrictive and electromagnetic force-induced vibrations were investigated. Simulations revealed that GO-PMSM exhibits 18.32% higher average torque and increased radial flux density due to anisotropic permeability. Experimental results demonstrated that the primary vibration sources are the 12th-order electromagnetic force harmonics (0th and 48th spatial orders) and the 10th/14th harmonics (8th spatial order). Notably, GO-PMSM shows significantly higher low-frequency vibration (below 1500 Hz) caused by magnetostriction in the teeth. This study highlights the trade-off between power density enhancement and vibration amplification in GO-PMSM, providing critical insights for high-performance motor design.

A V_AQ-based DAC switching scheme is proposed to improve the power efficiency of SAR ADCs. The input signals are sampled onto bottom-plates of the most significant bit (MSB) capacitors, thereby eliminating the reset energy. The reference voltage V_CM rather than V_REF is switched during the third-bit cycle, thus significantly reducing the power consumption. Additionally, an energy-efficient one-sided switching technique is employed from the fourth-bit cycle. This proposed switching scheme achieves a 99.51% reduction in switching energy over the classic scheme. The ADC with the proposed switching scheme is designed in 0.18-μm CMOS technology. It consumes 37.7 nW at a sampling rate of 20 KS/s and 0.6 V supply, and achieves the ENOB of 9.59 bits, resulting in a figure of merit (FOM) of 2.45 fJ/conversion-step.

A high-quality, high-yield integration of oriented M-type thick ferrite film with a SiC substrate through a simple and robust low-temperature thermocompression bonding technique is reported, solving the issue that ferrite devices, particularly ferrite circulators, cannot be integrated with planar RF circuits. Based on this bonding technique, a miniaturized self-biased circulator is successfully integrated onto a SiC substrate. This circulator, measuring 3.0 mm × 2.8 mm and operating at 35 GHz, exhibits a relatively low insertion loss of 1.2 dB, a bandwidth of 2.5 GHz, and a maximum isolation of 17 dB.

This paper proposes a scheme for applying space vector control method to a Switched Reluctance Generator (SRG) system with a ring winding structure. This paper focuses on the rectification system of SRG system, primarily analyzing the simulation model of the proposed system and the dual closed-loop control strategy for voltage and current. A solution has been developed to handle the strongly nonlinear and tightly coupled structure of the SRG when adopting the inner current loop control, and the issue of sector abrupt change that occurs when traditional control strategies are applied to the SRG system has been resolved. The performance of the SRG with a ring winding structure under different control strategies is compared in Simulink, verifying the effectiveness of the control strategy. Finally, the authenticity of the proposed control strategy is further validated on an experimental platform.

The globalization of the semiconductor supply chain has created new challenges for security researchers. Hardware Trojans (HTs) are considered to be one of the most difficult challenges. This paper presents an effective HT detection method based on power side-channel features that can classify circuits under test (CUTs) into Trojan-inserted (TI) and Trojan-free (TF). It classifies the power traces based on the machine learning algorithms. The selected machine learning algorithms include supervised and unsupervised algorithms. The experimental results demonstrated on AES benchmarks show that the accuracy of TI power traces is 91.38% and 65.81% with supervised and unsupervised machine learning, respectively. Finally, it uses majority voting to perform the secondary classification on the CUTs based on the classification results of the power traces, which can mitigate the effects of process variations and noise. The experimental results show that the secondary classification can achieve 100% and 94.44% accuracy of TI circuits with supervised and unsupervised machine learning, respectively. The effect of dataset balance on machine learning performance was investigated, and a balanced dataset can improve accuracy by 13% to 30%. The experimental results on AES 8/128-bit HT demonstrate the effectiveness of the proposed method in detecting unknown Trojans.

This paper reports p-channel metal-oxide heterostructure field-effect transistors (MOSHFETs) based on p-GaN/GaN/Al_0.29Ga_0.71N heterostructures grown by metal-organic chemical vapor epitaxy (MOCVD) on Si substrates. The two-dimensional hole gas (2DHG) density in the p-GaN/GaN/Al_0.29Ga_0.71N heterostructures is 1.3×10¹³ cm^-2 and remains unchanged down to a temperature of 80 K. A reduction of the GaN channel thickness by dry etching renders the p-channel MOSHFET enhancement-mode (E-mode) with a negative threshold voltage (V_th). The E-mode p-channel MOSHFET realized by GaN (18 nm)/Al_0.29Ga_0.71N shows a threshold voltage V_th of -0.79 V, an on-current |I_ON| of 2.41 mA/mm, a low off-state drain-source current (|I_OFF|) of 2.66×10^-9 mA/mm and a low subthreshold swing (SS) of 116 mV/dec. Such ultralow |I_OFF| and SS indicates high-quality epitaxial material. The high-temperature operation capability of the p-MOSHFET is evaluated up to 200 °C.

Power obtained from ultra-small energy harvesters is often tiny and difficult to use. The circuits with high power consumption can be driven by temporarily storing that power in a capacitor for a long time and discharging it instantaneously. We propose a unique intermittent-drive CPU that can operate even if the supplied power is minimal and intermittent. Regular CPUs are reset when power is turned off, so they are reset after every intermittent drive. This is because the regular CPU assumes a stable power supply. To enable intermittent and low-power operation, the amount of power required for CPU operation consumed at one time is reduced by executing only one CPU instruction cycle at a time. After instruction cycle processing, only the information necessary to continue the operation is stored in nonvolatile memory and read back when needed in subsequent cycles. This method does not save all data simultaneously, as in the sleep operation, but saves the data by dividing it frequently. Therefore, it has the advantage of low instantaneous power consumption and does not require special devices such as nonvolatile Flip Flops. We implemented an intermittent-drive CPU using the RISC-V RV32I instruction set architecture on an FPGA and a chip fabricated in a 0.18 um standard CMOS process. The designed chip was intermittently driven successfully with 6kHz power and reset signal.

In this letter, a rasorber with an ultra-wide electromagnetic (EM) wave absorption bandwidth is proposed, which is composed of multiple layers of indium tin oxide (ITO) resistive films with different structures and a metal ground. The rasorber has an absorption rate of over 90% at 1 GHz - 21.2 GHz under different polarized waves vertically incident, with a relative bandwidth of 182 %. When EM waves are obliquely incident, it can maintain an absorption rate of over 80% in the range of 45 °under TE and TM polarization, with angular incidence stability. An improved genetic algorithm was used to optimize the rasorber performance during the design process. An array prototype of the proposed structure is fabricated for testing and the experimental results match the simulation. The proposed rasorber belongs to EM metamaterials, with a cell period size of 0.167λ_L and a thickness of 0.1λ_L, offering advantages in miniaturization and low-profile.

To meet the demands of 5G base stations in large PAPR signal environments, this paper presents the design of a 550W improved three-stage Doherty power amplifier with a 12 dB back-off range. GaN HEMT devices with gate widths of 18 mm, 27 mm, and 27 mm are selected for internal matching design to ensure ultra-high output power. The paper analyzes the active load modulation mechanism under an asymmetric architecture and proposes an impedance matching design method suitable for this configuration. Test results in the 2.5-2.7 GHz show that the linear region gain is between 10.5 and 13.4 dB, the saturated output power ranges from 57.2 to 57.6 dBm, and the saturated drain efficiency is between 69% and 73%. At a 12 dB power back-off, the drain efficiency is between 55% and 58%. When the power back-off is 6 dB, the drain efficiency ranges from 62.2% to 65.1%. After incorporating Digital Pre-Distortion (DPD) technology, the ACPR test result is -55.9 dBc. These results address the issues of insufficient back-off range and linearity degradation due to saturation, which are common in traditional three-way and three-stage Doherty power amplifiers.

This paper reports a waveguide for terahertz electromagnetic wave transmission, featuring a complex multilayer stepped bend waveguide. The waveguide was fabricated on a silicon wafer using deep reactive ion etching, which had better mechanical performance compared to Silicon-On-Insulator based etching. After etching, the wafer underwent gold plating, low-temperature bonding, and dicing to produce the silicon waveguide, overcoming the integration challenges and slow processing of metal based waveguides. The experimental work focuses on investigating the key fabrication parameters that influence the waveguide’s transmission performance, as well as optimizing the Bosch process for etching the multi-layer stepped structure. Finally, an analysis was conducted on the differences between the measurement and simulation results. Results showed that the insertion loss of the waveguide was about 0.5 dB within the 300–530 GHz, achieving low-loss terahertz electromagnetic wave transmission.

In this paper, a smart system monitoring sensor based on a 12-bit SAR ADC with hybrid DAC is presented, and fabricated in a standard 55-nm CMOS process. By utilizing a MUX to switch the input channel, monitoring of the temperature and voltage at critical points is achieved. Additionally, a double conversion method is also proposed for circumventing the current mismatches of the two BJT temperature sensing elements, thereby lower the circuit complexity. For temperature sensing, the sensor shows a measured inaccuracy of ±1.5℃ from -55℃ to 125℃ with an resolution of 0.86℃. For voltage sensing, the ADC shows a measured DNL and INL of +0.43/-0.47LSB and +1.4/-1.1LSB, respectively. Thanks to the proposed technique, the sensor consumes low power of 182μW under a 1.8/1.2V supply at a conversion speed of 156kS/s, and occupies an area of 0.074mm².

This study presents the relation between transmission cross section (TCS) and directivity (D) of a narrow slot in an infinitesimally thin and perfectly conducting screen. Although TCS is recognized to increase proportionally with increasing D according to 2Dλ²/4π, this paper shows that TCS is not proportional to D in the imperfect transmission. The resonant transmission (RT) factor defined by D, 0≦K_RT≦1, was used to explain the transmission quality related to TCS and D. The perfect-RT (K_RT=1) occurs at the first resonance slot length as a perfect parallel resonance and leads to perfect transmission. In this perfect-RT, TCS is equal to . However, the imperfect-RT (K_RT＜1) occurs at the second resonance slot length and thereafter as an imperfect resonance and leads to imperfect transmission. In this case, TCSs are not equal to 2Dλ²/4π due to the imperfect resonance caused by the stored reactive power.

To solve the problem pertaining to voltage overshoot arising from frequent switching in CAN transceiver interface circuits, and to mitigate electromagnetic interference while protecting the circuit, this paper proposes a new low-voltage overshooting CAN transceiver interface circuit based on a 0.18μm BCD. The high-voltage switching transistor is controlled by comparing the bus voltage with a reference voltage to achieve real-time monitoring and protection of the bus voltage. The simulation results show that the interface circuit has excellent power consumption, anti-interference ability, and signal integrity, with a power consumption of 24.2μA and bus voltage symmetry of 0.934-1.052 under the passive state of the bus.

Mel-frequency cepstral coefficients (MFCC), an FFT-based speech feature extraction (FEx) algorithm, is a significant power consumer in low-power keyword spotting (KWS) chips. This work presents a KWS chip with an energy-efficient FEx, with an expanded-3bit-twiddle FFT (E3bT-FFT) algorithm which reduces power of FFT by 5.7x. Meanwhile, a multiplier-free MFCC (MF-MFCC) is proposed, effectively eliminating power-hungry multipliers and reducing the MFCC computational load by 7.3x. Fabricated in a 65-nm CMOS process, the chip occupies 0.17 mm² and consumes 2.3 µW, with the computation unit in FEx consuming just 76 nW, and achieves 94.9% accuracy on a 1-Word KWS with Google Speech Commands dataset (GSCD).

In this paper, an Efficiency Optimization Strategy (EOS) is proposed to address the issue of low efficiency in the Dual Active Bridge (DAB) DC-DC converter across certain power ranges under wide voltage conditions, with the aim of further enhancing the converter's efficiency over a broad operating range. First, in the low power range, a phase-shift control strategy is introduced, which enables wide-range Zero Voltage Switching (ZVS) and near-optimal inductor current RMS values. Through this strategy, ZVS is ensured for all switches under light load conditions, while under medium load conditions, ZVS is lost for only two switches. Subsequently, in the high power range, the optimization target is smoothly transitioned to the optimal RMS current value by utilizing the natural ZVS characteristics of the DAB converter. The operating range of the EOS is effectively extended, further reducing current stress and RMS current values, thereby achieving global efficiency optimization of the DAB converter. Finally, an experimental platform is constructed for verification, and the correctness and effectiveness of the theoretical analysis are confirmed by the experimental results.

While CNT FETs have been demonstrated to exhibit excellent resistance to irradiation, the radiation effects in complex environments remain relatively understudied. This paper investigates the synergistic effect of CNT FETs under the combined action of ionization and displacement damage using proton irradiation. It was observed that the V_th degradation (0.06 V) induced by 40 MeV protons was twice that (0.03 V) induced by 70 MeV protons with the same ionization dose. The numerical simulations indicated that the 40 MeV proton irradiation results in the formation of displacement defects in closer proximity to the semiconductor channel. This increased the hole capture rate, leading to a higher concentration of fixed charge in the SiO₂ layer and a larger threshold voltage shift.

In this work, gate leakage behavior on Schottky-type p-GaN gate AlGaN/GaN HEMT is investigated, especially when the Schottky junction is damaged. A controllable degradation of the Schottky junction is achieved, then the previous semi-floated p-GaN is electrically connected to the gate electrode. Therefore, the pre-stressed GaN device exhibits an improved gate stability, as well as a normal gate control and large gate swing. Furthermore, the associated trap level is extracted by Arrhenius plot based on the exponential relationship between the recovery speed versus temperature.