We have developed a novel fine-pitch multilayer wiring technology for wafer level packages using mechanical grinding. In this process, a dielectric film containing a rubber filler was first laminated and then cured over electroplated Cu posts. Second, the dielectric layer was subjected to mechanical grinding in order to expose the Cu posts. Finally, a Cu layer was deposited on the dielectric layer using electroless plating. Here, in order to improve the adhesion between the dielectric layer and the Cu layer, the dielectric layer was exposed to oxygen plasma and then chemically treated with a coupling agent. From this study, we found that the rubber filler enhances the adhesion strength between the dielectric layer and Cu wirings. Also, we successfully fabricated fine-pitch wirings with line/space of 5 μm/5 μm with the new process using the new dielectric film.

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The present paper proposes high-speed laser plating for forming wire-bonding pads on a Cu leadframe using Ag nanoparticles. The novelty of the process lies in the implementation of drop-on-demand laser plating on the specially designed leadframe. Various aspects of the proposed method are investigated, including experimental set-up, multistep ink-jet printing, laser-plating parameters, quality of the sintered film, and wire bondability. It is found that both the quality of the sintered Ag pad and wire bondability are comparable to those of an electroplated Ag film when the near-infrared CW laser irradiates the pad for a short time of milliseconds. The superiority of the high-speed laser plating is confirmed from the viewpoints of material consumption, the necessity of pre- and post-processing, thermal damage to the pad and substrate, and environmental protection.

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In order to improve the mechanical properties of a Cu–Sn alloy at elevated temperatures as well as the heat-resistant properties of said alloy, the effects of adding a small amount of zirconium were investigated. It was clarified that the addition of zirconium increases the tensile strength and elongation properties after a high-temperature heat treatment, and the addition of more than 0.04% zirconium increases the tensile strength to approximately 300 MPa. For a seamless tube, the tensile strength of a Cu–0.65Sn–0.05Zr–0.008P (mass%) alloy was 301 MPa, with an elongation of 47%. Furthermore, it exhibited high heat-resistant properties after brazing. Thus, it is expected that the Cu–Sn–Zr–P alloy can be used to make seamless tubes for heat exchangers.

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Sn–3.0mass%Ag–0.5mass%Cu (SAC) solder, which is widely used in Japan, has a relatively low impact reliability. This is because of the solder alloy hardness which induces a high stress concentration at the interface between the solder and the substrate. The impact reliability of the solder joint can be controlled by changing the composition of the under-bump metallurgy (UBM). This study aimed to determine the effect of electroless Co–P plating on the impact reliability of the solder joint using SAC, SAC–0.05Co and SAC–0.2Co solders. The intermetallic compound (IMC) layer formed at the interface between the three types of solder and the electroless Co–P plating was thinner than that of the SAC and electroless Ni–P plating. The hardness of the solders with electroless Co–P plating was lower than that with electroless Ni–P plating. The impact test results show that the solder joints with electroless Co–P plating are better at absorbing impact energy than SAC/Ni–P.

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Recently, differential-signaling (DS) techniques such as low-voltage differential signaling (LVDS) have come into wide use in digital electronics devices to suppress electromagnetic interference (EMI). In this paper, we attempted to newly identify the frequency responses of the EM radiation from a PCB driven by LVDS, using three EMI-antenna models. EM radiation is modeled and analyzed as EMI antennas, which depend on the configuration of the PCB. The first EMI antenna is a loop type due to the signal current flowing on the paired lines (EMI antenna I). The second EMI antenna is comprised of the ground plane and cable for a dipole type antenna due to a common-mode current flowing along the PCB with cable (EMI antenna II), and the third EMI antenna is comprised of the trace on the ground plane for the loop-type antenna due to the signal current (EMI antenna III). It is demonstrated that the larger EMI antenna, which consists of the ground plane, is the dominant horizontal-component radiation factor at the lower frequencies. The proposed model can explain the characteristics of EM radiation from a PCB driven by differential signaling and also identify the primary radiation factor. The antenna model provides enough flexibility for different geometrical parameters and increases our ability to provide insight and design guidelines.

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Flexible Printed Circuits (FPCs) have been commonly utilized for electric gadgets such as Liquid Crystal Displays (LCDs). Direct-Metallization is a promising method for plating highly conductive copper onto the polyimide films when fabricating the FPCs. In this paper, we suggest a two-step reduction process to improve the adhesion between the polyimide film and the precipitated copper metal with an enhanced mechanical interlocking effect. The peel strength of the metalized polyimide-based film is improved from 0.3 to 0.8 kN/m by adopting this process. Observation of the boundary structure between the copper metal and polyimide film reveals that the precipitating small and uniformly-sized copper particles are distributed just below the surface of the polyimide.

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The simplicity of the ink jet process has led to major changes in electronics packaging in what is known as printed electronics. Major changes here means drastic cost reduction relative to the long-term trend, and also creating a new performance axis (flexibility, customization, large area, little environmental load … namely added value). However, simplicity has two sides: `Possibility' and `Limitation.' For the past several years, `Possibility' has been attracting a lot of attention, but in the coming years, if ink jet technology does not overcome `Limitation', the real change will never occur.
In this paper, the related issues and status of approaches resolved by ink jet printheads or the printing process are described for the further progress and practical application of printed electronics using ink jet technologies.
These issues can be categorized into 1) ejecting processes of functional liquid, 2) drop landing and dot (film) formation on the substrate, and 3) maintaining printhead reliability. In particular, expanding the range of applicable liquids, further miniaturization of the ejected liquid drop, and improved accuracy of dot positioning are strongly required for printheads. In printed electronics, unlike with desktop ink jet printers, impermeable media are often used, so analysis and control of the behavior of the liquid on the substrate are also important. Furthermore, technologies for maintaining stability in the ejected drops make a difference.
These novel activities for improving ink jet issues will face tough problems and need revolutionary approaches, but a great innovation in printed electronics using ink jet technologies can be expected when success is achieved.

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Trace elements are increasingly being incorporated into lead-free solder compositions. This paper analyses the distribution of trace elements in solder joints when commercial purity Sn-based alloys are soldered onto Cu substrates. Analysis techniques include μ-XRF (X-ray fluorescence) mapping performed at the SPring-8 synchrotron radiation facility. The mapping results indicate that Ni is present in the Cu₆Sn₅ intermetallic reaction layer, and is distributed in a relatively homogeneous fashion as (Cu,Ni)₆Sn₅. In alloys containing trace levels of Ge (60 ppm), this element is comparatively concentrated within the oxide at the solder surface, and a lower concentration is distributed homogeneously in the solder matrix and the intermetallic reaction layer. In Sn–Pb alloys, the Pb was found to segregate to the boundaries between adjacent Cu₆Sn₅ grains.

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The warpage mechanism of a thin embedded LSI package with a thick Cu plate was investigated for various Cu plate thicknesses. The package warpage increased gradually as the Cu plate was made thinner. Even structures with a balanced Cu and resin layer configuration for the top and bottom portions of the embedded chip showed substantial warpage, especially in the chip region, that was greater than that for an unbalanced layer configuration. This indicates the existence of other warpage factors as well as unbalanced residual stress between the top and bottom of the chip. A `Birth & Death' finite element method simulation showed that the thermal residual stresses induced by the coefficient of thermal expansion mismatch for the LSI chip and embedding resin were concentrated in the resin surrounding the lateral sides of the chip and that the stresses increased with decreasing Cu thickness. The release of these tensile stresses resulted in package warpage.

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An array of Nano-protrusions (NPs) was fabricated on silicon surfaces in air and a low pressure environment using pulsed laser irradiation. The uniformly sized NPs were linearly aligned at a low laser energy density, which is typically a few kilojoules per square meter. The linear array of NPs appeared perpendicular to the laser polarization vector E, and the interval of the NPs lines was almost equal to the wavelength of the incident laser. The primary NPs grew epitaxially and were covered with an oxide film layer, which was determined by means of a structural and elemental analysis using scanning electron microscopy (SEM), transmission electron microscopy (TEM), and energy-dispersive X-ray spectroscopy (EDS). We propose a nano-patterning fabrication method using the laser-induced NPs alignment based on a microscopic structural analysis.

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A study of wafer-level hermetic bonding using sub-micron gold particles with a mean diameter of 0.3 μm was conducted at bonding temperatures of 150–200°C with varying bonding pressures in the range of 50–100 MPa. 4.5 mm-square, 10 μm–100 μm-wide sealing line patterns of sub-micron Au particles were formed on glass wafers by means of wafer-level processing using photolithography and a slurry-filling technique. The tensile bond strength was measured with a stud-pull method using 5 mm × 5 mm chips and exhibited as > 20 MPa. A preliminary hermeticity test was performed by immersing the bonded wafer pairs into a low-viscosity liquid and it was confirmed that the sealing lines with widths as thin as 20 μm showed a good sealing property against the liquid. The result demonstrated the feasibility of this low-temperature wafer bonding process using sub-micron Au particles, which could achieve hermetic sealing with absorbing a micron-level surface roughness and/or topography.

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Cu is gaining a lot of attention as the main wiring material for next generation devices. However, Cu oxidizes in high-temperature heat treatments. For heat-proofing considerations, a Cr/Cu/Cr system is widely used. Currently, the required Cr layer is too thick and Cr is environmentally problematic. Therefore, we focused on the stable oxide, SnO₂, and were able to increase heat proofing by covering Cr/Cu/Cr with SnO₂. This was able to tolerate a heat treatment of 873 K for 1800 s in air. 873 K is the highest temperature in the PDP manufacturing process, which has an especially severe heat treatment for various devices. However, some oxidization along the grain boundary was observed. In order to further increase reliability, we then investigated the elucidation of an oxidation mechanism. We show clearly that Cu crystal grain growth is the most important factor for the oxidation. Based on this fact, we tried to control grain growth and improve heat proofing by inserting one or more Cr layers into the Cu layer. The result looks like a mille-feuille or Napoleon pastry. As a result, grain growth was controlled and heat proofing greatly improved.

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In recent years, with the miniaturization of electric devices, the demand for flexible printed circuits (FPCs) using polyimide has increased, because of its excellent heat resistance and size stability. Polyimide also has good flexibility and surface smoothness. However, polyimide absorbs moisture readily and is highly permeable to gas. In contrast, Cyclo Olefin Polymer (COP) has low moisture absorption, excellent size stability and excellent high frequency electrical properties. Therefore, COP is attractive as a substrate for FPCs. However, it is difficult to form a metal film using electroless plating on the COP with conventional processes. We could form a copper film with high adhesion strength while maintaining a smooth resin surface by modifying the surface using UV irradiation. Surface modification by UV irradiation was effective to achieve good adhesion (about 1.0 kN/m) between the COP resin and the deposited metal without roughening the COP surface. The interface electric conductivity of the printed circuit on COP produced by this method indicated a value of approximately 80% up to around 30 GHz.

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Electroless Au/Ni plating is intensively applied to high-density printed boards. In this process, local corrosion often occurs between the deposited nickel and the deposited gold. Generally, nickel tends to diffuse from the local corroded areas to the deposited gold surface after thermal treatment due to its strong affinity for oxygen. These areas cause surface mounting failures. Recently, electroless Au/Pd/Ni plating has been actively studied as a substitute for electroless Au/Ni plating because it suppresses the nickel corrosion reaction. In this study, we investigate the influence of the nickel microstructure and the thickness of the palladium and gold on wire bondability. The wire bonding strength is increased with increased palladium and gold film thickness. The deposited nickel microstructures also influence the wire bonding properties after thermal treatment. It was confirmed that good wire bonding properties can be achieved using a nickel film with a layered microstructure rather than a columnar microstructure. From the AES analysis, we confirm that preparation of a uniform layered microstructure of the nickel film is a key factor to keep the gold concentration on the gold film surface after thermal treatment.

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Printed circuit boards (PCB) using Ajinomoto build-up films (ABF) as insulating layers are widely used as package substrates. Along with the increasing demand for downsizing electronic devices with advanced functions, package substrates are strongly required to be miniaturized with high-density circuit wirings.
The manufacturing method for multilayer PCBs using ABF is a semi-additive process including the lamination and curing steps of ABF resin composition, laser via formation and then desmear process accompanied with roughening the ABF surface prior to electroless copper plating as a seed layer to electroplate a thicker copper layer. The high adhesion between the plated copper and ABF insulating layer depends mainly on an anchor effect; however a smooth surface is desired for fine line formation, for example, of less than L/S = 15/15 microns.
Recently, we've developed very thin copper transfer films consisting of a supporter film, an alkaline-soluble resin layer, and a thin copper layer (150–1500 nm thick) deposited by vacuum evaporation or sputtering. In this paper, we report on the applications of very thin copper transfer films for both build-up PCB and core materials. With regard to build-up applications, the combination of a new ABF that has a low coefficient of thermal expansion and a high Young's modulus is demonstrated as a high-tech resin coated copper (RCC) film for fine line formation. Furthermore, the combination of very thin copper transfer film and ABF-prepregs, which are glass-cloth materials impregnated with ABF resin compositions, are proposed for use as core materials, especially for CSP substrates.
These new applications can achieve the high adhesion between the copper and insulating layers without anchor effects and that mechanism is presumed from the analysis of its interface using XPS. In addition, reliability tests were performed under the stress conditions of reflow tests and HAST.

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To remove dust particles accumulated on pad surfaces or probe tips after they contact each other during semiconductor wafer testing, a cleaning process is required. On the one hand, scrubbing is an efficient method to remove the oxide layer on the surfaces. However, excessive scrubbing degrades the probe's mechanical properties and leads to the accumulation of excessive dust and plastic deformation failure of the pad surface. Therefore, we have developed a new contact probe that allows only a vertical displacement of the probe tip on the pad surface to minimize the horizontal displacement for scrubbing. This probe is fabricated using a beryllium-copper alloy and is characterized by a two-beam structure. The matrix method is employed to investigate the contact probe structure and the results are compared with the data obtained with a commercial finite element method. Furthermore, electrical contact resistance is measured experimentally and determined theoretically using Holm's theory. A durability test is conducted to simulate more than 100,000 contacts between the probe tip and the pad; this allows us to examine the probe tip's endurance and whether the electrical resistance of the contact could be sustained. Our results suggest that the two-beam structural probe ensures a stable electrical contact resistance when the contact force is within specific limits and the horizontal displacement for scrubbing is minimized.

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In recent years, an innovative 3D-integrated circuit has been developed. Furthermore, innovative chip test technology has also been developed whereby the test is conducted without the need to dice the wafer. Chip tests must be performed at various temperatures. The 3D-integrated circuit has a higher heat generation density than a conventional circuit, and so highly efficient cooling technology is required. We selected an indirect spray cooling technology. With indirect spray cooling, there is a material between the heat generating chips and the sprayed coolant. Therefore, to achieve more efficient spray cooling, the thermal resistance of the material and the contact thermal resistance between the material and the chip must be reduced. In this research, we focused on super thermal conductive composites (STC) to reduce the thermal resistance of the material. Measurement results showed that the thermal resistance of STC is very small and the key issue with the spray cooling chip test is the reduction of the contact thermal resistance between the material and the chip surface. We then evaluated the contact thermal resistance of silicon with a mirror-like finish experimentally. We applied a small amount of liquid between silicon wafers with a mirror-like finish and obtained a very small contact thermal resistance of about 0.2 × 10^–4 m²K/W.

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The authors produced a demonstration electric vehicle, "Deep Green Research," based on a Honda Civic, in which critical electrical connections were soldered with a lead-free Sn–Cu–Ni–Ge alloy. This paper reports on the team's participation and completion in the Global Green Challenge, the world's largest solar car and eco car race, from Darwin to Adelaide, Australia that was run in late October, 2009. The successful completion of this course under the harsh conditions of the Australian outback proved the high reliability of the Sn–Cu–Ni–Ge lead-free solder joints in the control panels, cables, and connectors that had to carry the heavy current required to propel the vehicle over long distances at speeds of up to 104 km/hour. The vehicle set a new record for the longest distance travelled on a single charge by a car that satisfies relevant Australian safety regulations. This distance of 360 km was achieved using lithium-ion batteries with a total capacity of 33 kWh and resulted in an award in the category "Modified Production Class — Small Car (Electric)".

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To realize higher wiring density, both finer line/space resolution and a smoother resin-metal interface are needed. These requirements, however, conflict to each other: sufficiently fine lines are difficult to form on a rough surface, while a smooth surface generally results in poor peel strength. The feasibility of various metallization processes that promote adhesion on smooth resin surfaces is examined. Their practical applicability to manufacturing high wiring-density packages is also assessed and the related issues that need to be improved are discussed.

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Needless to say, an LED (light-emitting diode) is a semiconductor light source and LEDs are used as indicators and display elements in various devices. During the past few decades, the light intensities of LEDs have increased a great deal; therefore, white LEDs in particular are increasingly used for lighting.
For more than thirty years, the author has been doing research on applications of LEDs other than such conventional utilizations. His applications are novel and original. Furthermore, they are extensively applied in the fields of engineering, science, horticulture, agriculture, medicine, fishery and various LED commodities. In this paper the author will introduce his pioneering research on his LED applications.

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