An improved method for connecting flexible printed circuits and indium tin oxide (ITO) electrodes is proposed in this paper. The adhesives used were composed of a thermosetting resin and a thermoplastic resin. The test sample consisted of a polyimide base flexible printed circuit, (FPC). Non-conductive film (NCF) was pre-laminated on an ITO-glass and the test sample was then thermally bonded to the glass. The contact resistance between the ITO-glass and FPC was measured by a 4-probe method. A Cu wiring on the FPC was chemically etched, followed by selective electroless Ni–P deposition using hydrazine and sodium hypophosphite as reducing agents; Au film was then plated onto it. Since this method does not create extraneous deposition, it is one of the most promising candidates for future fine connection manufacturing processes. With lines and spaces of 75 μm and 75 μm, insulation resistance of 1 × 10⁸ Ω remained constant at 60 °C, 90 %RH, 30 V for 60 hours. Various FPCs with different line and space combinations have been investigated by the same method. The lines and spaces of 15 μm and 25 μm, 20 μm and 20 μm, and 25 μm and 15 μm show contact resistance of 2.02 Ω, 1.26 Ω and 0.844 Ω, respectively. Therefore, this method is intrinsically suitable for fine pitch FPCs with high reliability.

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A multi-chip module (MCM) was fabricated using an excimer laser driller and electro-plating. This method contributes to the interconnection properties of the MCM. First, a second chip with a thickness of 50 μm was mounted on a wafer that had been created by a wafer process, and polyimide with a thickness of about 100 μm was applied by a spin-coater to cover the mounted chips. Two types of via-holes, with depths of 50 and 100 μm, were formed by the excimer laser to connect the wafer and mounted chip pads. The excimer laser driller with a micro-lens array formed two types of via with diameters of about 30 μm simultaneously. Damage caused by the excimer laser irradiation was examined by direct laser irradiation of the FET transistor gate. Properties of the FET transistor did not change even after 500 pulses of 400 mJ/cm² which is sufficient for via-hole formation. A micro-lens array was designed to shorten the via-hole formation time. After via-hole formation, a seed-layer of sputtered Ti and Cu films were necessary, followed by copper electro-deposition. Microscopy measurements confirmed that the seed-layers were uniformly formed from top to bottom of the via-hole. Generally the mixture of additives to complete the via-hole filling consists of brightener, leveler, and a suppressor. By controlling the leveler concentration, a via-hole with a diameter of 30 μm and a depth of 100 μm was perfectly filled by copper electroplating. In this way the multi-chip module was created by wafer-level chip size technologies (W-CSP) using an excimer laser driller.

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The effect of shear speed on the ball shear strength of Sn–3wt%Ag–0.5wt%Cu solder ball joints has been investigated. The effect of electrode type on shear strength under various aging conditions was also studied. A linear relationship was obtained between the logarithm of shear speed and the ball shear load in the joints with Cu electrodes, regardless of aging conditions. Fracture occurs in the solder at lower shear speeds (below 10^–3 m/s) in joints both with Cu and with electroless Ni–P/Au plated electrodes. The fracture mode changes from a solder fracture to an intermetallic compounds (IMC) fracture at higher shear speeds (above 0.5 m/s), regardless of electrode type. This means a ductile-to-brittle transition exists in the shear speed range from 10^–3 m/s to 0.5 m/s. In the case of the joint with the Ni–P/Au electrode, shear strength decreases at higher shear speeds (above 0.5 m/s) due to the ductile-to-brittle transition.

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Our previous studies showed that co-deposition of refractory metal improves the properties of Ni–P films, so in this study we examined electroless Ni–W–P and Ni–Mo–P alloy films as alternatives to Pd films. High heat-resistance is necessary in the intermediate layer of printed wiring boards. The ternary Ni alloy films exhibit high heat-resistance properties. These new intermediate layers were evaluated from the viewpoint of wire-bonding strength. Results indicate that the new intermediate layers have almost the same properties as Pd intermediate layers and lamination. The experimental results also show that the ternary Ni alloy films suppress local corrosion, and Ni diffuses to the Au surface in the same way as a Pd intermediate layer.

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A new process to achieve a flat fine conductor pattern on LTCC green sheets is proposed in this paper. Conventionally, the screen printing method has mainly been used to form the conductor pattern on LTCC green sheets. However, it has become difficult to achieve further miniaturization using this method. In the method proposed here, photo resist film on PET is exposed to form arbitrarily designed patterns as the first step. Next, the conductor pattern is formed by filling the resist grooves with conductor paste. The resist is dissolved, and the specimen is then coated with LTCC slurry. Through these processes, a fine conductor pattern with a flat surface is formed on the LTCC green sheet. Using this new method, the authors obtained a fine pattern in which the lines and spaces were 20 μm. A through-hole also was created using a similar method.

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A defect analysis of high electron mobility transistors (HEMTs) was performed using the scanning electron and laser beams induced current (SELBIC) system. An electron gun and two infra red (IR) laser sources with wavelengths of 1064 and 1400 [nm] were located coaxially. Electron and laser beams were irradiated to a GaAs substrate from the reverse side through a quartz window. Two-dimensional current images between gate and source electrodes were observed during the scanning by the 1064 [nm] IR-laser beam under non-biased conditions. The area in which the current changed was observed on the gate electrode, and current leakage was measured from I-V characteristics. The image obtained by simultaneously using two laser beams with wavelengths of 1064 and 1400 [nm] showed different contrasts for each current change.

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This paper reports on an investigation of the fundamental transmission characteristics of the microstrip line in a Cu/BCB multi-layer fine wiring structure with a line width and space of less than 10 μm on a silicon core substrate. By measuring the S-parameter and analyzing the elemental contribution of the dielectric loss, we determined that BCB has better high frequency electrical characteristics than other dielectric materials. Transmission loss was divided into dielectric loss and conductive loss by theoretical fitting of the experimental results. The ratio of dielectric loss versus conductive loss obtained by our fitting analysis is in good agreement with that of our model. The following facts have been revealed: 1) Transmission loss is not greatly dependent on the width of fine wiring. 2) Much of the transmission loss depends on conductive loss caused by the skin effect. 3) When using low dielectric constant materials as the dielectric layer, conductive loss rather than dielectric loss dominates the transmission characteristics.

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Chip on Glass (COG) technology is widely used to mount driver ICs on Liquid Crystal Display (LCD) substrates. This paper reports the development of Resin Core Bump technology as a novel COG technology. Unlike conventional COG bonding with Anisotropic Conductive Film (ACF), Resin Core Bump structures form stable interconnections by direct contact between the bump and the substrate. Moreover, the bump and its bonding structures are optimized to achieve a fine-pitch interconnection. Pitches as fine as 10 μm have been attained with 40 μm-pitch samples. In this study, we evaluated the fine pitch bondability and interconnection reliability of Resin Core Bumps using 20 μm pitch test samples. The ability to compensate for bonding accuracy by shrinking the bump width was also evaluated. Reliability was evaluated by a thermal cycle test. The initial contact resistance was even more stable than with a 40 μm conventional COG structure. The maximum resistance increment was less than 2.0 Ω after 2000 cycles.

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This paper describes the design considerations for a high electric power density IGBT module structure mounted with smaller, new-generation chips. We have investigated heat flow depending on the copper foil thickness of an alumina based direct-copper-bonding (DCB) substrate, junction temperature rise in relation to the chip arrangement, electromagnetic noise dominated by the cupper circuit pattern, and lead-free solder layer stress as affected by the coefficient of thermal expansion (CTE) of DCB.
Low thermal resistance was obtained by using a 0.6 mm thick copper DCB substrate; consequently the CTE of the DCB increased to 16 ppm/K, which is nearly equal to that of the Cu base as a heat sink. The thick copper DCB substrate can lower the junction temperature of a small chip with a high electric power density and can improve the thermal cycling capability of the DCB substrate mounted with a lead-free solder on the Cu base. Moreover the thick copper circuit effectively reduces the electromagnetic noise generated on the DCB substrate. Thus we have successfully realized a high electric power density IGBT module structure.

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Packaging technologies such as BGA and CSP are now widely used to fabricate high-performance IC packages with ever-increasing degrees of miniaturization. In addition, electroless Ni/flash Au plating is now seeing wide-spread application because it offers improved solder wettability, etc. on electrodes. However, P tends to concentrate at the interface between the solder and Ni electrode, thereby reducing the joint strength. Despite several studies concentrating on plating methods and solder compositions, no solution to this problem has yet been found. However, through investigations on the use of various soldering fluxes, we successfully mitigated this decrease in joint strength by using a special flux containing Cu when joining solder balls to electroless Ni/flash Au-plated lands. Cross-sectional observation of the solder/electrode interface confirmed that the thickness of the concentrated P layer was reduced by the proposed method. We believe that the Cu ions contained in the flux acted as a barrier to the diffusion of Ni into the solder, thereby limiting the formation of a concentrated P layer.

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