We have developed a modified accumulated damage model that can be used to predict fatigue failure lives of solder joints in electronic devices. Our model calculates the fatigue failure life of solder on the basis of the damage that accumulates during crack propagation by using a finite element method and corrects for the dependence of element size on the calculated life by using the Hutchinson-Rice-Rosengren singularity theory. We predicted the fatigue lives of conventional and copper-core solder bump joints in ball-grid-array packages in thermal cycling tests. The good agreement between these predictions and experimental results indicates that our model can effectively predict fatigue failure life in solder joints.

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Copper wiring formation on a resin material with a low dielectric constant, a low dielectric loss and a smooth surface is indispensable to realize high-frequency signal propagation with fine wiring patterns. Cycloolefin polymer (COP) resin is a promising material to meet these requirements. We propose adhesive copper seed layer formation on the COP by magnetron sputtering as an alternative to the electroless deposition which usually requires an intentional roughness-induced process to obtain practical adhesion between the resin and the metal. The proposed process steps include plasma nitridation of the COP surface, thin CuN film deposition and Cu film deposition before the electroplating. Excellent adhesion strength between the COP and the metal, greater than 1 kN/m, can be obtained while maintaining a smooth surface, which is attributed to the strong chemical bond generated between the nitrided COP surface and the CuN film. The coplanar transmission line was fabricated using the proposed process steps with semi-additive processes, and we found that the introduction of relatively high-resistive CuN film does not cause degradation of the propagation characteristics.

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New material technologies for screen printing electronics were studied. A novel conductive paste which can be metallized at 180°C under reactive gas condition was developed using needle-shaped copper compound particles without any dispersant, protective agents or binder resins. The obtained conductive trace of dense 1.5 μm thick Cu layer with a crystal structure showed the volume resistivity of 2.4 μΩ·cm and excellent reliability. The metallization mechanism and excellent electrical performance were concluded to be different from those of the sintering.

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In this paper, an electrical test method is proposed to detect and locate open defects occurring at interconnects between two dies in 3D ICs. The test method utilizes a test architecture based on IEEE 1149.1 standards to provide a test vector to a targeted interconnect. Also, a testable design method for the IC is proposed for our testing. In this paper, testability of the electrical testing is evaluated using a SPICE simulation. The simulation results show that a resistive open defect of 100 Ω can be detected at a test speed of 1 GHz. Also, the test circuit is implemented inside a prototype IC. It is experimentally examined whether open defects between the IC and a printed circuit board can be detected by the test method. They are detected at a speed of 10 MHz by the test method in the experiments. It promises that interconnect open defects in a 3D IC can be detected by the test method per an interconnect at a test speed of at least 10 MHz.

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The physical and structural properties of the ferroelectric capacitors on a releasable substrate were shown for the clarification of effective process parameters in the fabrication of high-density capacitors. A Ti-bonding layer located at the corner is found to be effective for the prevention of the destruction during the crystallization process. The tensile stress of the capacitor films is caused by the deflection of the film surface. The crystallized capacitors have a perovskite structure and the same characterization as that on the non-releasable substrate. This paper describes the preparation process and also the estimation of the capacitors for the nano-transfer method. In this study, the releasing property of the thin film was evaluated as an important factor in this process. To evaluate the releasing property of the thin film, a tape test was performed and the conditions of the deposition and substrate were considered for PZT.

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Adhesion of the SiCN barrier layer and Cu film interface is one of the important characteristics that reflect the interfacial structure. NH₃ plasma treatment of the Cu surface is a well-known way of improving adhesion. The results of X-ray reflectivity (XRR) and X-ray photoelectron spectroscopy (XPS) depth profiles indicate that the plasma treatment imparts a difference to the formation of the interface with SiCN. Adhesion properties are regarded as fracture energies measured by double cantilever beam (DCB) and 4-point bending (4PB) techniques. The influence of the NH₃ plasma treatment of the Cu surface on adhesion is quantitatively discussed. The treated samples showed approximately twice the fracture energy of the non-treated samples. After 4PB and DCB measurements, fracture surfaces were investigated by XPS and atomic force microscopy (AFM). The formation of a N-Cu chemical bond on the Cu surface was enhanced as a result of removing oxygen by the plasma treatment. N-Cu chemical bonding contributes substantially to better SiCN/Cu interfacial adhesion.

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We studied the effects of 172 nm Xe₂* excimer lamp irradiation on polyethylene terephthalate (PET) surfaces. Two kinds of techniques were applied: vacuum ultraviolet (VUV) light irradiation and VUV irradiation in the presence of oxygen gas (VUV/O₃). The modified PET surfaces were investigated by using contact angle measurements which enabled the surface free energy to be calculated, X-ray photoelectron spectroscopy (XPS), nano-thermal analysis (nano-TA), and atomic force microscopy (AFM). The surface free energy increased significantly after the treatments. The results of XPS analysis showed that the elemental ratio of oxygen on the surface increased, whereas that of carbon decreased. From the deconvoluted C1s and O1s spectra, it was revealed that new oxidized functional groups such as alcoholic and carboxyl groups were generated. The nano-TA results showed that a low melting temperature (T_m) layer had formed on the VUV and VUV/O₃ treated PET surfaces. The results of AFM measurements showed there were no remarkable changes after the treatments compared with untreated PET. In summary, the VUV and VUV/O₃ treatments using a Xe₂* excimer lamp not only change the surface functionalities but also reduce the T_m of the PET surfaces without significantly affecting the surface morphologies.

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Coreless substrate is excellent for fine patterning, small via pitches, and transmission property, and it is a promising IC packaging method for the next generation. Warpage of coreless substrate is generally large compared to the other types of IC packaging substrates because of inadequate rigidity, so the most important problem for the application of coreless substrates for high-end BGAs is warpage reduction during a reflow process. So far, only a limited number of reports have been focused on coreless substrates for large size IC packages. Moreover, very few examples have discussed substrate layer structural designs for warpage reduction and reliability improvement in IC assembly processes. In our study, we focused on the development of coreless substrates for large size ICs. To achieve our goal, we adopted the following development procedure. First, we designed analytical models with different layer structures composed of two kinds of insulating materials and estimated the effective layer structures for warpage reduction by numerical analysis. Next, we prepared the real coreless substrates with the same structure as the analytical models and evaluated their actual thermal behavior. Finally, we investigated the thermal stress reliability of IC mounted substrates. As results of these examinations, we successfully developed low warpage and high reliable coreless substrate by introducing high rigidity materials only in the external layers of the substrate.

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Thermal structure function is a proven methodology to do experiment based structural analysis of heat path inside electronics package or cooling devices. However, how to understand the 3D heat flux structure from a 1D structural function is always the most difficult job for thermal engineers. In this article, 3D CFD software is used to describe the transaction image from 1D structure function to 3D heat flux distribution.

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A sub-channels-inserted porous evaporator is proposed as a heat sink for future power electronic devices with a heat load exceeding 300 W/cm². The porous medium is made by sintering copper particles of micrometer size in diameter and has several sub-channels to enhance discharge of generated vapor outside the porous medium. This porous heat sink is attached to the backside of a heating chip and removes the heat by evaporating a cooling liquid passing through the porous medium against the heat flow. In order to prove the validity of the sub-channels, the heat transfer characteristics of this porous heat sink are evaluated experimentally. The result shows that the heat transfer performance of a sintered-copper particles porous medium with sub-channels enables the removal of much higher heat flux under a lower flow rate of cooling water and a lower wall superheat conditions than those of a normal porous heat sink. The removal heat flux, 810 W/cm², is 1.8 times higher than that of a normal porous heat sink at a wall superheat of 50 K. Furthermore, it is clarified that even with a heat flux up to 810 W/cm², it is possible to sufficiently cool the SiC-based chip in practical use.

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A two-chip stacking 3D IC with 0.18 μm technology has been mounted in a QFP package for conducting measurement of thermal resistance from junction to the package case surface (bottom). The thermal resistances for the layers of chips, micro bumps, underfill resin between chips, and ceramic substrate are also being analyzed with the thermal RC model theory and the cumulative structure function. The top chip is embedded with through-silicon vias (TSVs) and is thinned down to 60 μm thick. The bottom chip has no TSV and the thickness is the same as a normal IC chip. Both chips have the same layout and include two types of heaters. The first heater is designed to emulate a hot spot and is located at the chip center. The second heater, with heat flux level (uniform heating) close to 1/20 of the first heater, is designed to heat up the surrounding area of the first heater. A simulation model of the QFP package is developed and a set of equivalent thermal conductivity correlations in planar (xy) and vertical (z) directions of TSVs are used in order to simplify the simulation model and shorten the computational time. Comparisons between simulation models show that the result is accurate for uniform heating condition and satisfactory for hot spot heating condition.

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This paper covers results from early pathfinding investigations of a wafer level package (WLP) technology that addresses future direct chip attach (DCA) needs. An overview of the WLP technology and pathfinding results covering key process flow evaluations and future challenges to apply the concept to DCA are presented. Proof-of-concept (POC) of 300mm wafer-level mold integrating with Cu bumps was demonstrated by investigating the mold thickness uniformity, wafer warpage, and solder joint reliability on the board. We conclude with a discussion of the key risk areas remaining challenges that includes the mold grinding thickness variance control, optimization of the material properties, and alternative low cost bumping technologies scalable less than 0.3mm pitch, and outline the next steps to continue data collection on the wafer warpage behavior, the die breakage strength, and the board level assembly process using a standard surface mount infrastructure in our pathfinding work.

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MEMS devices such as piezoelectric devices are being used for various purposes in recent years. At the same time, silicon wafer diameters have been expanding for the purposes of mass production and cost reduction in the manufacture of these devices. Therefore, it is becoming more difficult to prepare a dielectric film with homogeneous thickness and electrical properties on the wafer. Generally, physical vapor deposition (PVD) methods such as sputtering are said to be comparatively reproducible for preparing films on large wafers, but these methods require expensive equipment. Metal organic decomposition (MOD), a chemical solution deposition (CSD) method, was used to form a PZT (Pb(Zr,Ti)O₃) film on the 4-inch wafers in this study because it does not need expensive equipment such as a vacuum system. To improve the ferroelectric properties of the film formed using the MOD method, we optimized the process parameters using design of experiments methods and found that temperature is the most significant control factor. A PZT film was prepared homogeneously on 4-inch wafers under optimum conditions. Furthermore, a more homogeneous PZT film was prepared by making the temperature uniform using a soaking cover. We think that these results can be applied to the preparation of films on larger wafers as an alternative to PVD methods, which are currently the main method of preparing dielectric films but which require expensive equipment.

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To increase the productivity rate of the 3 dimensional system in package (SiP) used for electronics devices such as cloud computing and smart phones, the authors have developed a new micro solder flip chip bonding process. By this means, a higher-function and lower-cost SiP can be achieved. In the conventional process, more than 10 seconds of bonding time are needed to control metal oxide film of solder bump and the warpage of a thin chip. The paper suggest a flip chip process should be divided into the following processes; 1) the temporary bonding process i.e. the molten solder is rapidly diffused into an electrode under an inert gas atmosphere, and 2) the final joint process i.e. the solder bumps of multiple chips are all together bonded, while the warpage of chips are corrected under reductive gas atmosphere and pressure. The authors have verified that even when the fluxless process is used, such divided mechanism can shorten the time needed for bonding an IC chip with pitch and thickness of each 50μm to 0.25 seconds.

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As data transmission rate increases, flip chip plastic ball grid array (FCPBGA) utilizing an interposer for multiple chips is gaining prominence because of high performance. The authors assessed interposer configurations with a set of chip and package assumptions and obtained key parameters for mechanical analysis. The authors studied warpage of interposer, first principal stress in the dielectric layer under the controlled collapse chip connection (C4) bump pad, and von Mises stress at the solder joint between interposer and organic substrate with Si, glass, and organic interposers. The analysis results indicate that the stress under the C4 bump is very low with Si or glass interposer compared to conventional FCPBGA. Also, the results indicate that glass interposer with coefficient of thermal expansion (CTE) of 6 ppm/°C has approximately 30% lower stress than Si interposer at the solder joint between the interposer and the organic substrate.

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The structure and fabrication method are provided for a multilayer ceramic inductor with a suppressed magnetic flux path between the internal conductors. Magnetic flux passing between the internal conductors is a problem for conventional multilayer ferrite inductors. To solve this problem, the magnetic material and non-magnetic material should be placed and patterned in the same layer of the multilayer ceramic inductor. Conventionally, each layer has been composed of a single material. Therefore, it is difficult to form a pattern of different materials in the same layer. Using the process we have developed, it is possible to form an empty through pattern of different materials in the same layer using photo resist film. Using this method, we produced an inductor in which a pattern of the non-magnetic LTCC (Low Temperature Co-fired Ceramics) insulation material was placed inside the ferrite layer. It is believed that the patterned non-magnetic material suppressed the magnetic flux path between the conductors. The size of the fabricated multilayer ferrite ceramic inductor was 3.36 mm × 1.63 mm × 0.98 mm.

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To enable System-in-Package (SiP) solutions for analog products with active ICs or in combination with MEMS, passives or other components, a stacked Wafer-level Chip Scale Package (WCSP) platform has been developed using Through-Silicon Via (TSV) technology to create the smallest form factor package. This paper describes the integration flow and the development of the wafer over molding back-end unit process, using a 3 mm × 3 mm test vehicle on a 100 μm thick 200 mm wafer. Wafer-level over molding is a key development item as it provides support to the thin TSV wafers through the subsequent processes of debonding, ball attach and package singulation. Various molding materials and processes (compression, screen printing, film) were investigated. Selection of the mold material is a challenge as it must meet multiple requirements of processability, warpage, debondability, saw-singulation, and chip picking-up. Experimental results how to reduce warpage and Si damage by saw-singulation, and modeling results for the different mold materials and the pros/cons of the various molding processes are explained.

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This year's ICEP was held as entitled "ICEP-IAAC (IMAPS ALL Asia Conferece) 2012" in Tokyo. It is extraordinary topics for Jisso (Packaging Technology) that electronics manufacturing center has been transferred from Japan to the east Asia. But, related all Asia Jisso conference had not been held in Asia area. Any way, the meaning of the first IAAC is great and IMAPS HQ had proposed the idea.

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