Flip chip plastic ball grid array (FCPBGA) utilizing an interposer for multiple chip stacks, so called 2.5D or 3D package, is gaining prominence in order to achieve the next generation high performance computing. The multi-tier stacking of Si chip, Si interposer and organic substrate induces complicated warpage behavior and stress at the micro joints during the joining process. The authors studied warpage behavior and thermo-mechanical stress of multiple chip stacks on Si interposer package with different thickness of top chip, different thickness of Si interposer, different middle chip stacks and different metallurgy of micro joints after joining of stacked chips on the interposer using finite element method (FEM). Thicker stacked Si chips and thicker Si interposer showed higher von Mises stress at chip-to-interposer joint. Comparing SnAg joint and CuSn joint, CuSn joint always shows higher stress than SnAg joint because of its higher elastic modulus.

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We have developed a fine-pitch wiring technology for a package substrate by introducing a chromium compound adhesion promotion layer on the surface of smooth epoxy resin. In order to apply this technology to the manufacturing of multi-layer circuit boards, new via formation process is investigated. The outline of this via formation process is as follows: First, a copper foil with an adhesion layer is laminated on the epoxy resin. Then, the copper foil is removed using a liquid etchant to leave the adhesion layer. Next, the adhesion layer is covered with a dry film resist (DFR) layer and then, CO₂ laser is exposed over the DFR layer to form via holes. The smear is removed using a plasma treatment. Finally, the DFR layer is removed. In this study, the effect of the plasma condition on the smear removal rate and that of the type of DFR remover on the adhesion layer are investigated. As a result, we find that the smear is effectively removed by the plasma treatment with an O₂/CF₄ mixture gas and that the amine-type DFR remover does not damage the adhesion layer. This will be a new via formation process with a high adhesion strength.

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A new methodology for inspection of through-silicon via (TSV) process wafers have been developed by utilizing the signal of diffracted light from the wafer, which will be suitable for 3D IC production. Near infrared (NIR) light should be applied for the inspection including defect observation at a large depth with chip-cost economy. Diffraction-based macroscopic inspection with NIR light demonstrates a good potential for in-line defect inspection, because it can detect small shape variations and/or defects by capturing the light as a one- frame image via an image sensor, not a special high-cost image sensor but a general high resolution CCD sensor. Our newly developed TSV inspection system exhibits a high sensitivity to 3D shape variation and a high throughput covering the entire wafer. This new technology should be essential for future 3D IC fabrication.

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The surfaces of the connector terminals used for electrical connection of components are electroplated with Sn, Au, or Ag in order to improve reliability. For electronic devices that require particularly high reliability, hard gold is used. The characteristics of gold deposits of various surface morphologies were examined. Gold films with increased surface roughness exhibited superior friction and wear properties without a large increase in contact electrical resistance after friction testing. Increasing the surface roughness also resulted in higher solder adhesion strength and improved corrosion resistance to sulfur dioxide gas.

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We have developed high-performance electric fans by applying features of the wings of living creatures. This paper proposes an air purifier sirocco fan blade that mimics the wings of a dragonfly. Air quality has increasingly attracted attention in Japanese homes, and one or more air purifiers are installed in almost 40% of all houses in the country. The purpose of an air purifier is to maintain air cleanness, and it is operated overnight. There is, however, the problem of the loud noise created by the fan, which also makes overnight operation inconvenient. To solve this problem, we adopted the shape of the dragonfly wing in the sirocco fan blade of an air purifier. As a result, a maximum reduction of 2.5 dB was achieved.

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This paper presents the design and implementation of an LED lighting module powered by a wireless power transfer system. The overall system achieves an efficiency of 82% with an output power of 36 W when the load resistance in the receiver is 30 Ω, which is the turn-on resistance of the LED lighting module. The transmitter of the system adopts Class-E power amplifier structure instead of Class-D, to decrease the number of transistors and its cost. The coils of the system are designed by electromagnetic coupling methodology and realized by Litz wire to reach high efficiency. Matching circuits between the system blocks are also discussed in this paper in order to obtain the excellent system performance.

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Flip-chip bonding has several advantages, such as high precision, high density, short interconnections, and small parasitic elements. However, creating reliable interconnections between chips and substrates is the key issue in flip-chip bonding. In this work, bonding states are investigated using test element group (TEG) dies with gold stud bumps. Ultrasonic bonding is applied to a substrate with longitudinal and lateral leads, and the die-pull mode is investigated systematically. For conventional flip-chip bonding equipment, the die-pull test shows different bonding states for longitudinal and lateral leads. However, we have developed a flip-chip bonder with a rotational vibration head, where the direction of the angle of the vibration with respect to the die configuration can be changed. For a head rotated to 45 degrees, uniform bonding is established on both the longitudinal and the lateral leads. A wide process margin for flip-chip bonding is obtained, with a high yield.

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3D processor-memory packages potentially offer very high performance due to short interconnects between the two chips. Current Package-on-Package (PoP) technology offers less than 300 interconnects between the processor and memory. To meet future bandwidth requirements of greater than 25.8 GB/s bandwidth at low power, wide IO memory in x512 configuration is expected. This memory requires more than 1,000 interconnects and current PoP technologies do not scale to meet these requirements. To address this problem, a new PoP technology called Bond Via Array (BVA) PoP is presented that offers very fine pitch (0.24 mm and lower) and high height/diameter aspect ratio (8:1 and higher). This is achieved by forming free-standing wire-bonds along the periphery of the processor chip and encapsulating the package leaving miniature posts projecting from the top of the package to be connected to the memory package. More than 1,000 interconnects can be formed within the same footprint as current packages. The BVA PoP process development, assembly and reliability test results are presented. The assembly and all reliability tests including Moisture Sensitivity Level (MSL) testing, on-board temperature cycling, high temperature storage, and drop tests were successfully completed. These results demonstrate that the BVA PoP is ready for high volume manufacturing.

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This paper describes the thermal properties of power Si MOSFETs. Recently, the thermal problems of driving devices have been gaining attention. The thermal design of semiconductor chips is important since the main heat source in a driving device is the semiconductor chips. Power Si MOSFETs, which are widely used as semiconductor devices in car electronics, have serious thermal problems, since they use high voltages. Therefore, the thermal properties of power Si MOSFETs must be studied in order to improve the reliability of the electronics. In this study, the thermal properties of power Si MOSFETs are discussed. To investigate these thermal properties, calculations are performed using electro-thermal analysis. From the calculations, a hot spot appears in the power Si MOSFET, and the hot spot temperature rises with increase in the applied voltage. Furthermore, the difference between the hot spot temperature and the average temperature becomes greater with the increase in applied voltage. The results indicate the risk of conventional thermal design with the assumption of uniform heat generation.

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Time domain reflectometry (TDR) is applied to the failure analysis of through-silicon vias (TSVs). The reflection time of the TDR signal from test-element-group (TEG) chips with TSVs stacked on a silicon interposer is compared to the distance between the failure point and the contact pad derived from a TDR simulation value, using a model which has the same structure as the TEG chips. These results show good agreement between the simulated and the measured results.

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We developed the reliable flip chip mounting structure of VCSELs without hermetic sealing to realize 14 Gbps transmission modules. Underfill resin is sometimes used to protect VCSELs when hermetic sealing is not applied. However, it was shown that cracks occur inside VCSELs if Young’s modulus of underfill resin is high. The cracks can be prevented if we avoid the arrangement of underfill resin of high Young’s modulus on the mesa parts of VCSELs. We considered two mounting methods to prevent this failure. The first method is to use underfill resin of low Young’s modulus. The other uses a structure where the air caps cover the mesa parts. We evaluated these methods and confirmed that the cracks do not occur in either case.

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This paper explores system level transient heat transfer behavior under natural convection cooling with slate style chassis assuming a tablet device design. Steady state analysis based on heat conduction simulation is conducted to see the effect on microprocessor silicon die temperature and skin temperature of the chassis by internal structure difference and determine final configuration for transient simulation. After that, transient state analysis is conducted assuming the case that a microprocessor starts running TDP (Thermal Design Power) equivalent application workload after system reaches steady state with static screen idle power consumed by the microprocessor.

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We have developed a Si interposer with multilayer 15-μm-thick Cu wiring and SrTiO₃ (STO) thin film capacitors to help create novel 3D stacked buck converters, which consist of a CMOS LSI that includes active components and a Si interposer with an LC output filter. A spiral inductor made using 15-μm-thick Cu wiring was stacked over an STO thin film capacitor in the Si interposer without any deterioration in capacitance and leakage current. A minimum line/space of 20 μm/20 μm and a minimum via-hole diameter of 30 μm were achieved to create 15-μm-thick Cu wiring patterns in the Si interposer. A newly developed chemically-amplified positive-tone resin was used as the interlayer dielectrics in the Si interposers to avoid under-exposure at the bottom of thick photo-sensitive resin and to obtain fine-pitch wiring patterns. The power efficiency of buck converters depends on the parasitic resistance of the embedded inductors. As a result, the 15-μm-thick inductor enhances the efficiency of an output current of 100 mA by 12% as compared to a 5-μm-thick inductor. The developed Si interposer with 15-μm-thick wiring layers will contribute to creating a 3D stacked buck converter for low-power and high-performance 3D integrated systems.

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The improvement of interconnection technology is becoming a top priority for the operation of SiC devices at high temperatures. We proposed a new interconnection method using nickel electroplating to form bonds between chip electrodes and substrate leads. We also newly proposed low-temperature nickel nanoparticle sintering to form die bonding connections. SiC devices assembled with these new connection methods operated successfully in a high-temperature environment of about 300°C. We confirmed that these methods had adequate potential as an advanced heat resistant package in comparison with conventional interconnections.

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In was deposited onto the joint interface of a Cu/Sn joint to examine the effect of the filler metal on the tensile strength of the joint and on the reduction of the bonding temperature. Observations were carried out using Scanning Electron Microscopy (SEM) to observe the interfacial microstructures and fracture surfaces. After the In filler was deposited onto the joint surface, liquid-phase diffusion bonding was carried out. Compared to a specimen that did not have the In filler, a specimen with the In filler could be joined with an approximately 30% lower degree of deformation and at a temperature that was approximately 30 K lower. At the same time, the achieved tensile strength was comparable to that of the base metal on which the In was deposited. Two possible reasons were considered for the increase in the tensile strength. First, when heated to 393 K, In and Sn react with each other and turn into a liquid phase. This layer of liquid then covers the entire bonding surface and increases the area of contact between the bonding surfaces, which in turn causes the increase in the bonding strength. Second, because In is easier to oxidize than Cu and Sn, the metallic In becomes In oxide, which is formed by the In taking oxygen from the native oxide films of the Cu and Sn. Subsequently, the intimate contact that is achieved between the metallic Cu and metallic Sn increases the bonding strength.

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Silver nanoparticle paste (SNP) was demonstrated to be a promising candidate as an alternative material to conventional silver electro-plating. The sintered film of SNP in a reductive atmosphere showed excellent bonding strength equivalent to the value of the silver electro-plated surface in gold and copper wire bonding. The silver hybrid paste (SHP) composed of micro and nanoparticles has been newly developed. SHP with 40 μm thickness exhibited low volume resistivity after sintering. The sintered film showed good wire bondability.

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We investigated the relationship between the conductivity of isotropic conductive adhesives (ICAs) and silver (Ag) particles (filler) that are coated with different lubricants; high molecular weight fatty acid. The components of the ICAs are organic epoxy binder and silver filler. The conductivity of the ICAs was measured by a milliohm tester and the electron charge between silver particles was determined by powder charge amount measurements. The conductivity of ICAs differs depending on the kind of lubricant used, and there is a possible correlation between conductivity and the charge amount of silver particle in the samples. These results suggest that the conductivity of ICAs is not only a result of connections between the silver particles, but also of some interaction between the lubricants and silver particles. The silver filler particles in the ICAs appear to function as micro-capacitors in the cured state.

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