Transactions of The Japan Institute of Electronics Packaging
Online ISSN : 1884-8028
Print ISSN : 1883-3365
ISSN-L : 1883-3365
Volume 12
Displaying 1-11 of 11 articles from this issue
Preface
Technical Papers
  • Taizo Tomioka, Ikuo Shohji
    Article type: Technical Paper
    2019Volume 12 Pages E18-013-1-E18-013-7
    Published: 2019
    Released on J-STAGE: April 16, 2019
    JOURNAL FREE ACCESS

    This paper describes the bondability of thermosonic flip chip bonding, in which ultrasonic (US) vibration perpendicular to the interface was applied. Experiments were carried out with a device chip having 11 Au stud bumps and a ceramic substrate having Au-plated bonding pads. The stud bump was used to investigate bondability when the bump was largely deformed. The height reduction ratio of the bump was changed from 38% to 64% by changing bonding load and US amplitude. The relationship between the height reduction ratio of bump and shear strength of the bond was compared with that using US parallel to the interface. It was found that the bonding using US vibration perpendicular to the interface requires bonding load and US amplitude above a certain level to obtain high bond strength. When the height reduction ratio of the bump became bigger than 60%, bond strength of approximately 100 MPa was obtained. This strength was higher than bond strength of the bonding using US vibration parallel to the interface.

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  • Ken Saito, Daniel S. Contreras, Yudai Takeshiro, Yuki Okamoto, Satoshi ...
    Article type: Technical Paper
    2019Volume 12 Pages E18-009-1-E18-009-7
    Published: 2019
    Released on J-STAGE: April 16, 2019
    JOURNAL FREE ACCESS

    Ideal microrobots are on the millimeter-scale with integrated actuators, power sources, sensors, and controllers. Numerous researchers are inspired by insects for the mechanical or electrical design of microrobots. Previously, the authors proposed and demonstrated microrobots that can replicate the tripod gait locomotion of an ant, the legs of which were actuated by shape memory alloy (SMA) actuators. The SMA provided a large deformation and force, but the power consumed by actuating a single leg reached as high as 94 mW. This paper discusses a silicon electrostatic inchworm motor chip to move a robot leg with low energy consumption using a small power source. The inchworm motor chip was actuated by electrostatic motors. The power consumption was as low as 1.0 mW, in contrast with SMA actuators. The reciprocal motion of the inchworm motor chip is powered by silicon photovoltaic cells. The results show that the 7.5 mm2 photovoltaic cells could produce 60 V to actuate the inchworm motor chip, and the generated force is enough to move the leg of the microrobot. Thus, we demonstrated the actuation of a microrobot leg using an electrostatic inchworm motor chip, which is the first reported instance of an electrostatic motor driving an off-chip structure.

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  • Daisuke Ogawa, Yoichi Sato, Yasutaka Wada, Kanji Otsuka
    Article type: Technical Paper
    2019Volume 12 Pages E18-008-1-E18-008-7
    Published: 2019
    Released on J-STAGE: June 28, 2019
    JOURNAL FREE ACCESS

    This paper is the progressive study of previous papers presented at the IMPACT 2015 and ICEP 2018, and evaluates effectiveness and applicability of MLCS (Memory Logic Conjugated System) with a simple deep learning processing. NVIDIA, Google, Fujitsu Intel-Altera, Intel-Nervana and Renesas recently announced that 8 bits processing can keep efficient and flexible AI computation, peculiarly in deep learning. This paper discusses on the actual MLCS circuit implemented on a commercial FPGA for deep learning, and evaluate the circuit with perceptron method for deep learning. In the MLCS architecture, deep learning computations can be done as memory operations. Our architecture can achieve its high I/O bandwidth and low-power consumption with dynamic reconfiguration functionality, high-speed connection among logics and memory cells, and low implementation cost.

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  • Akimasa Kuramoto, Yutaka Fukunaga, Yasushi Imoto, Yoshitaka Inaki, Sai ...
    Article type: Technical Paper
    2019Volume 12 Pages E18-003-1-E18-003-6
    Published: 2019
    Released on J-STAGE: August 29, 2019
    JOURNAL FREE ACCESS

    Novel aluminum nitride (AlN) fillers with large particle size and round shape were developed using the carbo-thermal reduction and nitridation (CRN) method in this study. They were used as high thermal conductivity fillers for resin composites. Thermal conductivity of epoxy resin filled with the AlN filler could reach 12 W/m K. The fluidity of the epoxy resin filled with the developed AlN filler was improved to 1.3 times that of conventional resin. Also, viscosity of silicon resin filled with the AlN filler was one tenth lower than the conventional AlN filler. The properties and evaluation of the developed AlN filler for high thermal conductivity packaging material have also been discussed.

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  • Masao Tomikawa, Akira Shimada
    Article type: Technical Paper
    2019Volume 12 Pages E18-007-1-E18-007-4
    Published: 2019
    Released on J-STAGE: September 27, 2019
    JOURNAL FREE ACCESS

    High thermal conductive adhesive having extreme low interfacial thermal resistance was developed for thermal management of power device and modulus. We focused on reducing an interfacial heat resistance between high thermal conductive sheet composed of resin and heat conductive filler and metal such as Cu or Al. The interfacial thermal resistance was determined by modulus of heat conductive sheet and dispersion of high heat conductive filler. The low modulus sheet and the good dispersed sheet showed lower interfacial thermal resistance. In addition, we investigated the effect of filler size. The larger filler size showed higher heat conductivity and higher interfacial thermal resistance. To consider the effect of those facts, we successfully developed the high thermal conductive sheet with extremely low interfacial thermal resistance. Bulk heat conductivity of the sheet is higher than 10 W/mK. The interface thermal resistance is below 0.009 K/W.

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  • Yasutake Koishi, Shuichi Ishida, Tatsuo Tabaru, Wataru Iwasaki, Hiroyu ...
    Article type: Technical Paper
    2019Volume 12 Pages E19-001-1-E19-001-14
    Published: 2019
    Released on J-STAGE: December 24, 2019
    JOURNAL FREE ACCESS

    Wire bonding is an important technique for forming semiconductor junctions, and statistical quality assurance is determined through sampling inspection. However, as the number of connections increases due to high semiconductor integration, wire bonding reliability becomes important, and connection evaluation is required for all products. In a previous study, we focused on the application of ultrasonic waves, which greatly influences the bonding strength of wire bonding, and proposed a quality estimation method using a thin film AE sensor and machine learning. In that study, samples made with manual wire bonders were destroyed by pull testing, and the quality was judged based on the fracture load. However, the loop shape of the manually prepared samples was not constant, and thus the results of the pull testing varied. In this study, we automated the fabrication of the bonding samples, stabilized the sample shape, and sought improvement in the quality evaluation performance. Since the number of defective samples was small, we developed a quality estimation method using a one-class SVM, an anomaly detection method involving machine learning. Experiments using actual samples confirmed that the accuracy rate in the proposed method was roughly 86%.

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  • Hiroki Seto, Kei Hashizume, Toshiya Murata
    Article type: Technical Paper
    2019Volume 12 Pages E18-014-1-E18-014-7
    Published: 2019
    Released on J-STAGE: December 24, 2019
    JOURNAL FREE ACCESS

    Compact electronic devices are created primarily using fine patterning technology. Electroless Ni-P/Au plating plays an important role in the metal finishing for these printed circuit boards. In this study, we evaluated new additives containing high-valent metal ions for electroless Ni-P plating to improve pattern forming ability. Conventional additives have caused step plating or poor corrosion resistance. But the addition of high-valent metal ions could prevent these problems. Also, our research indicates that the addition of Co3+ could most effectively prevent deposition on the area surrounding the pattern. We suppose that Co3+ reduces to Co2+ on Pd residues preferentially to the deposition of Ni. Therefore, deposition on the area surrounding the pattern can be prevented by the addition of Co3+.

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  • Tilo H. Yang, Yu-Shan Chiu, Ching-Yun Yang, Akitsu Shigetou, C. Robert ...
    Article type: Technical Paper
    2019Volume 12 Pages E19-012-1-E19-012-8
    Published: 2019
    Released on J-STAGE: December 24, 2019
    JOURNAL FREE ACCESS

    Joining of dissimilar materials is extremely important for flexible electronic packaging, which is generally achieved by assembly of pre-patterned electronic components into multi-layered architectures on soft organic substrates via transfer-printing technique. To avoid thermo-mechanical damages during bonding, organic- and inorganic-organic solid-state direct bonding must be achieved. Here we report a novel bonding process enabling both homogeneous and heterogeneous material hybridization at low temperatures. Vacuum-ultraviolet-induced reorganization of ethanol was used to achieve multiple effects of surface modification on organic and inorganic surfaces before bonding, which has been named ethanol-assisted vacuum ultraviolet irradiation (E-VUV) process. In this study, investigation of X-ray photoelectron spectroscopy (XPS) and transmission electron microscopy (TEM) was conducted to thoroughly understand adhesion mechanism. The analytical results proved that the E-VUV process was applicable to polyetheretherketone- and tin-polyimide bonding, and the bonded interfaces are expected to be robust enough for flexible electronic packaging.

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  • Shunya Saegusa, Ikuya Sakurai, Ikuo Okada, Takao Fukuoka, Satoru Suzuk ...
    Article type: Technical Paper
    2019Volume 12 Pages E19-003-1-E19-003-7
    Published: 2019
    Released on J-STAGE: December 24, 2019
    JOURNAL FREE ACCESS

    To achieve the three dimensional additive manufacturing process, we investigated X-ray radiolysis-induced photochemical reaction of Cu(CH3COO)2 solution. Here, we demonstrated synthesis and immobilization of copper and copper oxide particles onto an aluminium substrate directly from the liquid solution. The particles are formed in the X-ray radiolysis of flowing aqueous solutions of Cu(CH3COO)2 which also contain methanol as ⋅OH scavenger. We found that the sizes and compositions of the particles depend on the flow rate of solution. The results indicate that there are several routes and reaction processes for these particles formation and their aggregation. Our study will shed light on understanding and providing a novel photochemical reaction route induced under the X-ray irradiation. The development of X-ray radiolysis-induced photochemical reaction process enables us to achieve the rapid and easy formation of higher-order nano/micro-scale structures consisting of composite materials.

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  • Moritoshi Yasunaga, Shumpei Matsuoka, Yuya Hoshino, Takashi Matsumoto, ...
    Article type: Technical Paper
    2019Volume 12 Pages E19-007-1-E19-007-9
    Published: 2019
    Released on J-STAGE: December 24, 2019
    JOURNAL FREE ACCESS

    Signal integrity (SI) degradation in printed circuit boards (PCBs) in the gigahertz domain has become an increasingly serious problem because of the difficulty of developing and implementing impedance matching designs. In this paper, we propose a novel trace structure called a capacitor segmental transmission line (C-STL) and a design methodology for C-STL capacitances to overcome the problem of SI degradation. In a C-STL, reflected waves are intentionally generated by mismatching the impedance of adjacent segments with embedded chip capacitors connected to the PCB trace. These reflected waves interfere with the distorted digital signal and shape it into an ideal waveform. In the proposed C-STL design methodology, a genetic algorithm is used to overcome the combinatorial explosion problem posed by the chip capacitor selection required in the design. A C-STL prototype was fabricated, and its high SI improvement capabilities were demonstrated by eye diagram measurements.

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