The development of a novel mist-jet technology for ejecting a water mist containing silicon microparticles is described and demonstrated. A desired pattern can be drawn successfully on a large substrate using a silicon head specially designed for highly purified mist. The demonstration was performed using water containing silicon microparticles. The ejected mist droplet diameter was observed to be approximately 2.8 μm stimulated by an ultrasonic driving frequency of 5 MHz. The substrate was mobilized by a motorized stage at an optimum speed of 60 mm/s and a working temperature of 100°C for dehydration. The letters "BEANS" were drawn in silicon on a 200 mm × 200 mm glass substrate without any required surface treatment. A silicon-coated substrate was prepared by mist-jet ejection on a 10 mm × 10 mm area for thickness uniformity measurement using stylus surface profiler. The silicon pattern achieved uniformity to a standard deviation of 20 nm at a thickness of 380 nm.

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Recently, differential-signaling (DS) techniques such as low-voltage differential-signaling (LVDS) have been widely used in digital electronics devices in order to suppress electromagnetic interference (EMI). But in practical terms, a complete topologically and structurally symmetrical differential line is impossible. In this paper, we newly attempt to quantify the imbalance component and electromagnetic (EM) radiation when the structure and topology change from a symmetrical to an asymmetrical differential paired lines. Four different differential-paired lines structures are prepared for the comparison: PCB1 is a basic symmetrical structure taken as an "ideally balanced" case, PCB2 is an asymmetrical structure due to differences in bend and length, PCB3 is a symmetrical length structure with a bend region, and PCB4 is an asymmetrical topology with equi-distance and bend routing. Firstly, the differential voltages and mixed-mode scattering parameters are selected as a measure. The conversion parameter from differential-mode (balance component) to common-mode (imbalance component), S_cd21, is dramatically increased by the difference of the length. Even if the differential paired lines have a bend-region, equi-distance routing can suppress S_cd21. Secondly, spatial distributions of near magnetic fields are measured at certain resonant and out of resonant frequencies of S_cd21. Although the differential paired lines are excited by the differential-mode, propagated magnetic field component at the end terminal of the differential paired lines at the resonant frequencies of S_cd21 could be changed to the common-mode. Thirdly, the far-electric fields at 3 m are measured and calculated. Even if equi-distance routing is suitable for the improvement of signal integrity (SI) issues, it is not enough for the suppression of the far-field potential radiation. It is clear that S_cd21 is one evaluator but it is not sufficient for predicting the EM radiation completely. The facts shown in this study suggest the basic characteristics of EM radiation from practical differential paired lines with asymmetrical structure and some significant problems in the design of a meander delay line for high-speed clock distribution.

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The mechanical integrity of wirebonds are sensitive to structures under the bond pads of ultra low-k dielectric devices. The authors studied the mechanical performance of wirebonds on 32-nm test chips with various layouts of lines and vias under the 35-μm-pitch bond pads, various stacks of dielectric layers, and a range of bonding process conditions. Poor mechanical integrity resulted in the pad tearout failure mode at wire pull testing. The thickness of the SiO₂/FTEOS layer and the density of the vias in the ULK layer are the key factors for good wirebond integrity, manufacturability, and module-level reliability with ultrafine pitch wirebonds. The wirebond experimental results were analyzed by capillary indentation, excessive bond force parameter and finite element method (FEM). The authors found that only excessive bond force does not increase the rate of pad tearout and 2D FEM model can correlate the location of pad tearout in the ULK layers with calculated highest stress point which occurs by the ultrasonic vibration during wirebonding process.

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A novel Cu surface treatment method was developed to improve the adhesion between smooth Cu surfaces and epoxy dielectric layers using a silane coupling agent. In this process, the Cu surface was first modified with a functional group, which was then treated with the silane coupling agent. Here, we investigated the effect of the functional group and the silane coupling agent on the adhesion strength between Cu and epoxy dielectric layers. We also investigated the influence of the Cu/dielectric adhesion layer on smooth Cu wirings of the printed circuit board manufacturing process compatibility. From this study, it was found that two-step Cu surface modification with triazine trithiol followed by treatment of mercapto-group containing silane coupling agent would dramatically enhance the adhesion strength. It was found that a thin triazine trithiol layer was very effective to improve desmear-resistance.

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Scaling consideration is applied to the coupling electro-thermal characteristics of Si MOSFETs with device length typically larger than 100 nm. The non-equilibrium nature of the electrons and the crystal lattice is considered. Both lumped and rigorous electro-thermal models are deployed to examine the device thermal trend with device scaling. The lumped model considers the self-heating of the device and the resulting electron and lattice temperature rise. The results show that the non-equilibrium nature of electrons and phonons becomes important for devices with gate lengths typically shorter than 1 micrometer. Also, the lumped model showed an increase of the electron temperature due to the scaling trend even though the lattice temperature is kept constant. Further investigation of the heat generation characteristics revealed that hotspot predictions for devices typically shorter than 200 nm need different strategies than for larger devices.

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It is useful to be able to further miniaturize printed wiring boards (PWBs) to achieve more compact and multi-functional mobile electronics. Since about 40–50% of the surface of a PWB is covered with passive elements such as capacitors, it is clear that miniaturization would improve performance. On the other hand, PWBs have a low temperature resistance, and thus the boards cannot use capacitors that require higher processing temperatures. The nano-transfer method, which consists of release and transfer steps, solves this problem. After the capacitor is fabricated on a high-temperature-resistant substrate, it is released from the substrate and mounted on the PWB. The purpose of this study is to clarify the release process in order to establish a fabrication technology for embedded substrates.

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One method of miniaturizing electric boards is to reduce the capacitor area on the board. We fabricated a thin film capacitor on a Si wafer, released the capacitor from the wafer, and transferred the released capacitor onto a board. BaTiO₃ (BTO) was chosen as the dielectric material, and a capacitor was fabricated using metal-organic decomposition (MOD) onto a Si wafer with Ti and Pt as the bottom electrode. Measured electric properties included the dielectric constant, at about 640, as the I-V property, and hysteresis. When a BaTiO₃ film was deposited onto the substrate, which had only a Pt electrode (no Ti used for bonding layer) to release from the substrate after deposition, the electrode broke because of internal stress. The stress was measured quantitatively and a new electrode structure was designed to overcome the problem. ECR etching proved adequate for making the electrode structure.

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High signal integrity (SI) is strongly required in PCB traces under GHz clock frequencies for the next generation of VLSI packaging. Unfortunately, however, conventional techniques based on characteristic impedance matching cannot work well with GHz digital signals. In order to overcome this problem, we have previously proposed a novel PCB trace structure called "Segmental Transmission Line (STL)." In this paper, we design STLs for GHz bus-systems in which a high SI is indispensable, and demonstrate the high effectiveness of the STL showing the waveforms observed in the STL prototypes. Furthermore, the STL is analyzed in the frequency domain to demonstrate its mechanism of high robustness against frequency fluctuations.

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The heat transfer characteristics of copper minichannel-finned heat sinks are experimentally investigated in order to clarify their applicability as a single-phase flow cooling device for next generation power devices. The influence of the channel width and the fin thickness are evaluated in detail. In particular, the minichannel-finned heat sink having a channel width of 0.3 mm and a fin thickness of 1.0 mm achieves a heat transfer performance of approximately 70,000~9,5000 W/m²K at 300 W/cm² even in a single-phase flow heat transfer regime. Simple estimation proves that single-phase-flow heat transfer with the minichannel-fins heat sink is able to sufficiently cool future power devices under the allowable pumping power conditions.

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Nowadays, precise prediction of heat generation in semiconductor devices is important. An electro-thermal analysis is an attractive method to predict heat generation in devices. In this analysis, momentum and energy relaxation times are taken as the important parameters. Calculated heat generation density is dependent on the energy relaxation time. Conventionally, these relaxation times have been determined by simple models. For a more precise prediction of the relaxation times, Monte Carlo (MC) simulation should be employed. In this research, the impact of these relaxation times on the heat generation in a semiconductor device is evaluated. The results of an electro-thermal analysis using conventional relaxation times (conventional model) and of one using the relaxation times from a MC simulation (MC model) are compared. The calculation results show that the conventional model overestimates the heat generation density especially under a high electric field. The estimated heat generation density of the conventional model is 10% and 25% larger in the case of 100 and 500 kV/cm electric fields, respectively. It can be concluded that, for the thermal design of high-power semiconductor devices in power electronics, appropriate values of the relaxation times, which are obtained from the MC simulation, are required.

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Cooling capability is measured for a two-phase (vapor-liquid) flow-cooling system in terms of its thermal resistance and cooling power. The performance is compared between systems with and without a pump that drives the flow of a dielectric working fluid with a low boiling point. The geometry of the boiling chamber is first examined for each flow configuration to ensure the best possible performance. The results show that using a pump does not always result in higher power consumption than that of a thermal siphon system and the driving force generated by the pump augments phase-change heat transfer thereby reducing the fan power to minimize the overall power consumption. The present results show that the flow-boiling system has a high cooling capability using a small amount of cooling power compared with the thermal siphon.

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PoP (Package on Package) structures have been used widely in digital consumer electronics products such as digital still cameras and mobile phones. However, the final stack height from the top to the bottom package for these structures is higher than that of the current stacked die packages. To reduce the height of the package, a flip chip technology is used. Since the logic chips of mobile applications use a pad pitch of less than 80 μm or less, an ultra-fine-pitch flip chip interconnection technique is required. The C4 (Controlled Collapse Chip Connection) flip chip technology is widely used in area array flip chip packages. The C4 was named after the four initial characters which are "C" of Controlled Collapse Chip Connection. The collapse of the molten solder is controlled by the individual opening of solder resist on each pad on the substrate so that the chip can be connected onto the substrate. However, C4 is not suitable in the ultra-fine-pitch flip chips because the such a individual opening which is suitable for the ultra-fine-pitch cannot be made on the substraete. Instead of the C4 flip chip technology, the new interconnection technique was developed using the solder capped Cu pillar bumps. It is very easy to control the space between the die and the substrate by adjusting the Cu pillar height even when a large slit window opening exists on a group of pads on the substrate. Since the collapse control of the solder bumps is not necessary, we call the process C2 (Chip Connection). The C2 was named after the two initial characters which are "C" of Chip Connection. The solder capped Cu pillar bumps are connected to Cu substrate pads, which are a surface treated with OSP (Organic Solder Preservative), by reflow with no-clean processes. This technology creates the SMT (Surface Mount Technology)/flip chip hybrid assembly for SoP (System on Package) use. We have produced 50 μm pitch interconnections and observed the micro structure and tested their reliability. Some voids in the solder joint were observed after the reflow process. The results of warpage measurements and FEM (Finite Element Method) analyses suggest that these voids are the shrinkage voids caused by the wide temperature range of the solder liquid phase and the substrate warpage. Since they are not the stress induced voids, they didn't affect the reliability test. The increase in interconnection resistance during the reliability test was compared between the C2 interconnection and Au stud-solder interconnection. Since the resistance increase of the C2 interconnection is much smaller than that for the Au stud-solder interconnection, it is clear that the C2 flip chip technology provides robust solder connections at low cost. Also the C2 structure with a low-k device was evaluated and no failures were observed at 1,500 cycles in the TC (Thermal Cycle) test. In addition to the fine-pitch interconnections, a die thickness of 70 μm is required to reduce the final stack height. The reliability performance of the C2 flip chip with the die thicknesses 20 μm, 70 μm and 150 μm was also discussed using a PEG (Post-Encapsulation Grinding) method in which the die is ground to less than 70 μm after joining and underfilling. Finally the electromigration tests were performed on the 80 μm pitch C2 interconnection. The tests showed that the solder capped Cu pillar structure has high endurance against electromigration and no failure data was recorded up to 1,000 hrs with several electromigration conditions regardless the direction of electron flow.

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Plating on plastic technology is widely applied in electronics-related fields. Conventionally, good adhesion strength between metal and resin has been obtained from the anchoring effect of a roughened surface. However, as the frequency increases, detrimental influences arise from the skin effect in the high-speed transmission. Therefore, the interface of the conductor and substrate should be as smooth as possible. A metal film with high adhesion strength and surface smoothness can be formed by surface modification with UV irradiation. This led us to the examination of selective deposition with the UV irradiation technique. In addition, anisotropic growth has been obtained by the addition of inhibitors to the electroless plating bath where pattern formation was possible without using resist by controlling the horizontal growth during plating. Anisotropic growth on selectively UV-irradiated regions has been obtained by the addition of inhibitors to the electroless nickel-plating solution and in this study, direct nickel-pattern formation was accomplished without using resist by controlling the plating growth in the horizontal direction in a technique combining selective deposition and anisotropic growth.

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Peripheral flip chip interconnection on gold plated pads would be required to assemble the chip with surface mount technology (SMT) because the gold pads are sometimes used for SMT. Chip Connection (C2) which uses solder-capped copper pillar bumps on the chip and uses reflow process is an attractive method for ultra fine pitch peripheral flip chip interconnection. 50 μm-pitch interconnection on gold plated pads was made with C2 and the shape of the solder joints was discussed. It was found from a mechanical analysis that the stress in low-k layer would be reduced when the solder did not wet on the sides of copper pillars on the chip. Direct immersion gold (DIG) surface treatment would be attractive for not only compatibility to assemble with surface mount components but also for chip-package interaction improvement.

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Low-temperature joining with sintered silver is being developed as a lead-free, non-solder, die-attach solution for packaging power devices and modules. While its feasibility has been demonstrated, one major drawback of sintered silver joint is the high applied pressure during sintering to produce the desired bond strength. A high percentage of voids could also remain in the sintered joints. Applying the technique to large-area attachments also means a correspondingly higher applied pressure, and damage to the devices and substrates is possible. This study focused on the use of nanosilver paste as an attachment material that can be sintered at relatively low temperatures and pressures. Because of the difficulty of obtaining the die-shear strength of very large attachments, two non-destructive methods, micro X-ray computed tomography (CT) and curvature measurement using a laser-scanning technique, were used to characterize the bonded structures. Effects of different drying and sintering conditions on the bonding qualities were discussed.

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A palladium-nanoparticle/acrylic-polymer hybrid negative pattern was formed on a flexible film by photolithography and then converted to a copper pattern by electroless plating. The negative pattern of the hybrid was formed by UV-irradiation of the resist film, which contained acrylate monomer, palladium salt, and a photo-radical initiator. The photochemically generated radicals induced the radical polymerization of the acrylate and also reduced the palladium ion to form palladium nanoparticles. A copper film was deposited on the surface of the hybrid pattern by electroless plating, where the palladium nanoparticles work as a catalyst.

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New material technology for ink-jet printing has been studied. The relationship between new insulator ink and conductor ink was investigated. The fine pattern with highly adhesive performance was obtained by the simple process without any photomask. Experimental results revealed that the contact angle and the sliding angle are important parameters. The insulator ink was used for the insulating, surface leveling and material adjusting between the conductive traces. The new metallization process to fabricate the conductive copper trace was also investigated. The temperature of the process was below 200°C, which is suitable for organic substrates. The volume resistivity and pull-strength testing showed that the developed inks are applicable to fabricate highly conductive, smooth and straight patterns.

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The propagation delay of a logic signal through a through silicon via (TSV) in a 3D IC may depend on a soft open defect inside it. The propagation delay of a defective TSV which is connected only with barrier metal, in part owing to a soft open defect, is analyzed with an electromagnetic simulator and a circuit one in this paper. The results reveal that if such a soft open defect occurs inside a TSV, the delay depends on the defect size and the IC may work without any errors. A soft open defect will change into a hard open one in operation of a 3D IC and may generate a logical error. In order to realize high reliability of the IC, the defect should be detected before it changes into a hard open defect. In this paper, test input vectors are proposed with which a soft open defect can be detected by delay testing. However, the simulation results suggest that when the input and output capacitance of a TSV is small, the defect may not be detected even if the test vectors are provided to the defective IC, since the propagation delay of the defective TSV can be smaller than a defect-free one.

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Boiling heat transfer is a superior heat transfer technology using the latent heat transport with phase-change. However, it has been difficult to employ as a cooling technology for electronics because the unstable transition boiling and film boiling with excessive high temperature are impossible to control. In highly subcooled boiling, the coalescing bubbles formed on the heating surface collapse to many fine bubbles at the beginning of transition boiling and the heat flux exceeds the critical heat flux. This boiling regime has been called Microbubble Emission Boiling (MEB). Two models of cooling device are introduced using subcooled flow boiling with MEB for power electronics, where the maximum heat flux is 500 W/cm² (5 MW/m²).

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