On-Chip Power Noise Measurements and Simulation Technologies of Digital LSIs

Abstract

The dynamic power noise of digital large scale integration (LSI) has a major impact on LSI performance as well as on the electromagnetic performance of electronic systems. Accurate understanding of power noise generation, noise propagation, and their interaction with circuit operation are necessary in order to ensure correct design considerations. This article discusses power noise problems in LSIs and introduces on-chip noise monitoring and chip-level noise simulation technologies.