Journal of The Japan Institute of Electronics Packaging
Online ISSN : 1884-121X
Print ISSN : 1343-9677
ISSN-L : 1343-9677
2011 JIEP Award – Technical Development
Development of EMI Rule Check Tool for Supporting Printed Circuit Board Layout Design
Takashi HaradaManabu KusumotoTakahiro Yaguchi
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2011 Volume 14 Issue 6 Pages 477-484

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Abstract
An EMI rule-check tool, which provides a solution that can suppress undesirable electromagnetic radiation from printed circuit boards (PCBs), is described. At the placement design stage (pre-routing), this tool examines optimal placement locations for parts by using imaginary routing and verifies the effects of the proposed EMI solution. The tool has two main functions: EMI design rule checking, and power distribution network analysis. The first function scans the board layout against 13 rules and lists errors in order of priority allowing time efficient noise countermeasures. These rules have been obtained by investigating EMI mechanisms in boards. This tool can also suppress resonance between the power and ground (GND) planes by analyzing the resonance which occurs when changing the locations of capacitors. By eliminating the causes of unnecessary electromagnetic radiation from the initial design stage, this tool substantially reduces the time and costs needed for revision after the prototype is developed and enables a rapid time-to-market.
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© 2011 The Japan Institute of Electronics Packaging
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