An EMI rule-check tool, which provides a solution that can suppress undesirable electromagnetic radiation from printed circuit boards (PCBs), is described. At the placement design stage (pre-routing), this tool examines optimal placement locations for parts by using imaginary routing and verifies the effects of the proposed EMI solution. The tool has two main functions: EMI design rule checking, and power distribution network analysis. The first function scans the board layout against 13 rules and lists errors in order of priority allowing time efficient noise countermeasures. These rules have been obtained by investigating EMI mechanisms in boards. This tool can also suppress resonance between the power and ground (GND) planes by analyzing the resonance which occurs when changing the locations of capacitors. By eliminating the causes of unnecessary electromagnetic radiation from the initial design stage, this tool substantially reduces the time and costs needed for revision after the prototype is developed and enables a rapid time-to-market.

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An insulated metal substrate (IMS) is a circuit board comprising an insulating layer on a metal base plate. The insulating layer is made from epoxy resin incorporating dense ceramic fillers. The thermal conductivity of the insulating layer is calculated from measurements of the thermal resistance of the substrate. The influence of percolation on the thermal conductivity of an insulating layer is considered. The thermal conductivity as a function of the volume fraction of filler is estimated. Based on these experimental and numerical results, the equivalent thermal conductivity of the filler is evaluated. It is thought that the control of filler size and shape is important for the achievement of high thermal conductivity of an insulating layer. In addition, an improved equation for assessing the thermal conductivity of an IMS is proposed. The predictive values agree with experimental results.

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In this paper, we discuss diplexers using a wide-band filter and a SAW filter. The wide-band filter is fabricated in an LTCC substrate. We developed the diplexers for GPS/UWB and Bluetooth/UWB applications. The diplexers are evaluated with commercial simulators and also experimentally. Our results show that the GPS pass band (the range of 1.555 to 1.600 GHz) and the UWB pass band (the range of 3.23 to 5.13 GHz) are realized. We are able to produce the GPS/UWB diplexer at a size of 4.35 mm×5.225 mm×1.06 mm. Moreover, we realize the Bluetooth pass band (the range of 2.37 to 2.54 GHz) and the UWB pass band (the range of 3.23 to 5.21 GHz). For the Bluetooth/UWB diplexer, we achieved a size of 4.35 mm×5.92 mm×1.06 mm.

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We evaluated the high-frequency signal-transmission characteristics of fan-out interconnects integrated in a three-dimensional integrated-circuit (3D IC) structure built with SMAFTI (SMArt chip connection with FeedThrough Interposer) packaging technology. The S-parameter measurements of the interlaminar horizontal wiring up to 40 GHz confirmed the potential of this wiring for transmitting signals at speeds of over 10 Gb/s. We also evaluated the transmission losses due to transitions such as die-edge crossing, interlayer vias, and right-angled bends, and confirmed that these transitions had little impact on the signal transmission characteristics.

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This paper reports on our study of a fabrication process for polymer MEMS devices utilizing hot-embossing and polishing steps. In this paper, a PMMA thermal microactuator was developed and characterized to demonstrate the process's capability and robustness. In the hot-embossing step, a two-step silicon mold fabricated using bulk micromachining technology was used to create PMMA microstructures. Then, the hot-embossed structures were bonded to the PMMA substrate using a surface activation bonding method, and the back layer of the hot-embossed PMMA structure that remained after hot embossing was removed by a polishing step to release the movable microstructures. A V-shaped PMMA thermal microactuator with a thickness of about 50 μm was fabricated and tested successfully. The displacement was about 10 times larger than that of a Si counterpart at the same temperature difference.

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We have established a plating condition which shortens the plating time for through-electrode silicon vias with 10 μm diameters and 70 μm depths within an 8-inch wafer from 90 min to 60 min. We evaluated the microstructures after annealing as a function of plating conditions. It is found that the grain size of the plating films formed with conventional, i.e., high-pulse current density and low-duty cycle pulse conditions, are smaller than those for high-speed solution flow plating films. We also showed clearly that the diamond pyramid hardness number (H_v) of through-electrode Cu plating films is proportional to the square of the reciprocal of the grain size (d).

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