Journal of The Japan Institute of Electronics Packaging
Online ISSN : 1884-121X
Print ISSN : 1343-9677
ISSN-L : 1343-9677
System Design for AI Implementation
Hardware Implementation of a Brain Model on Wafer Scale Integration Technologies and Its Fault Tolerance
Moritoshi Yasunaga
Author information
JOURNAL RESTRICTED ACCESS

2022 Volume 25 Issue 5 Pages 404-410

Details
Download PDF (1814K)
Download citation RIS

(compatible with EndNote, Reference Manager, ProCite, RefWorks)

BIB TEX

(compatible with BibDesk, LaTeX)

Text
How to download citation
Contact us
Article 1st page
Content from these authors
© 2022 The Japan Institute of Electronics Packaging
Previous article Next article
Favorites & Alerts

Recently viewed articles
Predecessor

HYBRIDS

Circuit Technology

Journal of SHM

The Journal of Japan Institute for Interconnecting and Packaging Electronic Circuits

Related journals
Transactions of The Japan Institute of Electronics Packaging
Proceedings of JIEP Annual Meeting
Proceedings of Microelectronics Symposium
Share this page
feedback
 Top