Abstract
Since the interconnect delay has become the dominating factor in circuit performance, and the demands for a better delay-minimization router are very high. In this paper, we propose an algorithm for finding an interconnect tree of a net that minimizes a weighted sum τ of delays to all sinks, where the weight assigned to a sink represents a criticality of the delay to the sink. The algorithm starts from a Steiner tree and repeats a tree transformation while the change of τ is monitored. Experimental results are also shown, which demonstrates the effectiveness of the algorithm, especially for MCM and PCB routing.
