Since the interconnect delay has become the dominating factor in circuit performance, and the demands for a better delay-minimization router are very high. In this paper, we propose an algorithm for finding an interconnect tree of a net that minimizes a weighted sum τ of delays to all sinks, where the weight assigned to a sink represents a criticality of the delay to the sink. The algorithm starts from a Steiner tree and repeats a tree transformation while the change of τ is monitored. Experimental results are also shown, which demonstrates the effectiveness of the algorithm, especially for MCM and PCB routing.

View full abstract

Electrodeposited tin-indium eutectic alloy promises to replace tin-lead solder coatings in LSI flip-chip interconnections thanks to its lower melting point and provide superior in thermal fatigue resistance. Eutectic tin-indium alloy film was deposited at 0.5-3A/dm² and at 25°C, in a sulfosuccinate bath using the additives 2, 2'-Dithiodianiline, polyoxyethylene-α-naphthol and polyethlene glycol 1000. The coexistence of these additives markedly inhibited preferencial deposition of tin. The eutectic tin-indium alloy film consists ofβ-Sn, In, InSn₄ and In₃Sn phases, and its solidus temperture was 117°C.

View full abstract

Process capability for the fine tool processing was studied and the FEM analysis was done in order to clarify the tool strength demanded at the stamping. It was confirmed that the die inserts and the punches could be processed to 77μm in space and 74μm in thickness respectively by wire electric discharge and grinding machines. The process accuracy of die inserts processed by wire electric discharge machine using a wire of φ40μm diameter was determined. The process accuracy of punches processed by two different methods was found to depend on the processing. The effects of the curvature, fixing position and bending shape on the punches buckling strength were clarified by the FEM analysis. The results of the FEM analysis also showed that variations in the widths and step heights of die holes reduce the die inserts strength for the multipin shearing model.

View full abstract

In general, the solderability and bondability of electroless nickel (EN) deposits are greatly affected by the phosphorus contents in the deposited nickel films. This paper describes the phosphorus distribution and content in the EN films at both the initial stages and following steady state of deposition conditions.It was found that phosphorus contents in the deposits at the initial stages indicate higher values than the following steady state deposition. The highest phosphorus content in the films was obtained from the citric acid bath among the tested complexing agents. Phosphorus rich layer was formed at the top of the surface of EN deposits. And the P rich layer around 20 to 40nm is produced at the initial stages of deposition and this layer is always staid at the top of the deposited surface along with the progress of deposition reaction.

View full abstract

The compositions of the Sn-Ag alloy films obtained by the Sn/Ag-nanoparticle composite plating were near the eutectic composition, Sn-3.5wt%Ag, and were uniform over a wide current density range from 2 to 30mA/cm². Hardness of the electroplated Sn-Ag alloy films was higher than that of the thermally prepared alloys, and increased by the rapid cooling after melting. This hardness change was attributed to the change in the microstructure, that is, Ag₃Sn particles were more uniformly distributed when rapidly cooled. The bond strength of the solder ball onto the Sn-Ag alloy plated Cu was slightly smaller than that onto the Cu substrate when substrate surface was clean. However, the solder bond strength of the Sn-Ag alloy plated Cu was not decreased after the exposure to the humid environment, and somewhat increased by the Ni underlayer.

View full abstract

The effects of interfacial reaction on the joint strength has been investigated for QFP joints with Sn-l0Pb or Au/Pd/Ni plated Cu lead using lead-free solders such as Sn-3.5Ag, Sn-3.5Ag-0.7Cu, Sn-3Ag-5Bi and Sn-3.5Ag-2.5Bi-2.5In. High temperature exposure test and thermal cycle test were carried out. The joint strength depended on the thickness of the interfacial reaction layers consisting of Cu₆Sn₅ and/or Cu₃Sn. In the case of the joints using Sn-3Ag-5Bi solder with Sn-10Pb plated Cu lead, significant degradation of the joint strength occurred in the high temperature exposure test and the thermal cycle test. This is due to the rapid growth of the reaction layer, which is caused by the melting of Bi and Pb rich phase ahead of the reaction layer. All joints, except for those using Sn-3Ag-5Bi solder with Sn-l0Pb plated Cu lead, showed strength and reliability comparable to the Sn-37Pb eutectic solder joint.

View full abstract

Thermal residual stress and warp deformation behavior generates in a semiconductor device were analyzed, concerning with the material properties such as modulus, glass transition temperature and thermal expansion coefficient, using the numerical simulation method based on the thermo-viscoelastic analysis software we developed. In order to decrease the interfacial thermal residual stress between LSI chip and elastomer in a semiconductor device, it is efficient to use the elastomer of which properties are low modulus, high glass transition temperature and low thermal expansion coefficient.

View full abstract

We have proposed a new focusing/tracking error signal detection method using a holographic optical element (HOE), and reported the evaluation results with this HOE-LD/PD integration unit carried in the optical pickup. In this error signal detection system, focusing and tracking error signals are detected with sub beam spots generated by the HOE, and the main beam spot is used only for RF signal detection. For this reason, it is not necessary to use multi-segment PD for RF signal detection. Therefore, improvement of the RF signal response is expected to become easy. Basic operation of the optical pickup using this new HOE was examined experimentally, and good results were obtained.

View full abstract

The elution of bismuth, silver and tin into acid rain from three kinds of lead-free solder with different melting points (different proportions of bismuth) was investigated and com-pared with that of lead from Sn37Pb solder. The amount of bismuth eluted from lead-free solders ranged from approximately 1/100 to 1/3 of that of lead eluted from Sn37Pb solder, whereas the amount of silver eluted was less than 1/100 of that of lead. In contrast, the elution of tin from lead-free solders alloyed with much bismuth, which has a higher oxidation-reduction potential than tin, was more than that from Sn37Pb solder. The galvanic potential difference increased the elution of tin, lead and bismuth from solders joined to copper. Since eluted bismuth, silver and tin were easily changed to colloidal precipitate, it is considered that lead-free solder is unlikely to cause significant water pollution.

View full abstract

The deterioration of ball solderability is indicated with the narrower pitch of solder balls of BGA package. Accordingly, the tape carrier that the via-holes for the ball soldering were buried with copper plating was developed for the prevention. In order to deposit of the copper plating in minute blind via-holes of the polyimide tape, suitable copper sulfate plating bath at the thickness over 40μm was found. And, the analysis and control technique of additives as dispersing agent and brightener, etc. was also established. Uniformity of the current distribution in the plating tank was necessary for the small deviation of the copper plating thickness. In order to solve the problem, based on the computer simulation, the optimum current shielding board was installed in the tank, and the equalizing of the thickness was achieved. On the bases of these results, it was established the mass-production technology of uniformly and high-speed copper plating in minute via-holes which were formed on tape carrier of long length. And the continuous copper plating machine for tape carrier was constructed. For further miniaturization of the LSI package, the developed technology has been widely applied to the tape substrate.

View full abstract

Surface breakdown phenomenon of printed wiring board was investigated with increasing temperature from 23°C to 150°C. The experiment was carried out by do pulse voltage with the frequencies in the range of 50Hz to 150Hz. Printed wiring boards of epoxy resin laminate have been employed to investigate the effects of the surface temperature, electrode distance and the frequencies of applied voltage on the discharge quantity. The study revealed that the time to breakdown decreases with increasing the temperature, increasing the frequency of applied voltage and decreasing the electrode distance. The characteristics of discharge currents with increased temperature and the electrode distance were discussed by power spectral density of discharge current. The results show that the power spectral density of discharge currents increases with increasing the temperature, and decreasing the electrode distance.

View full abstract