Abstract
A three-dimensional (3D) chip stacking LSI under development at ASET uses new SiP (System-ina-Package) packaging technologies to realize high-density and high-speed transmission. Superfine flip-chip bonding microbumps on Cu through-via (TV) in 20-μm-pitch is another important technology to realize vertical interconnection. For an advanced and commercial chip stacking process, Cu bump bonding (CBB) utilizing Cu-Sn diffusion for simple connection of Cu TVs without the formation of bumps on the chip back surface was examined. We clarify the Cu-Sn diffusion phenomena on minute interconnections, and in terms of structural strength, the interconnection composed of a single Cu3Sn layer was most desirable. A temperature cycling test (TCT) was performed on the 3D chip stacking structure, and over 1500 cycles of reliability was confirmed. We conducted two important electrical evaluations. One was the DC resistance of the vertical interconnection, which was measured at only 15.4 mΩ per layer. The other was the signal transmission delay, which was confirmed at only 0.9ps. Therefore, the vertical interconnection formed by CBB demonstrates the excellent high performance interconnection capabilities of a 3D chip stacking package.
