The Benchmarking Working Group of IETF has defined a benchmarking methodology for IPv6 transition technologies including stateless NAT64 (also called SIIT) in RFC 8219. The aim of our effort is to design and implement a test program for SIIT gateways, which complies with RFC 8219, and thus to create the world's first standard free software SIIT benchmarking tool. In this paper, we overview the requirements for the tester on the basis of RFC 8219, and make scope decisions: throughput, frame loss rate, latency and packet delay variation (PDV) tests are implemented. We fully disclose our design considerations and the most important implementation decisions. Our tester, siitperf, is written in C++ and it uses the Intel Data Plane Development Kit (DPDK). We also document its functional tests and its initial performance estimation. Our tester is distributed as free software under GPLv3 license for the benefit of the research, benchmarking and networking communities.

Diffusion least-mean-square (LMS) is a method to estimate and track an unknown parameter at multiple nodes in a network. When the unknown vector has sparsity, the sparse promoting version of diffusion LMS, which utilizes a sparse regularization term in the cost function, is known to show better convergence performance than that of the original diffusion LMS. This paper proposes a novel choice of the coefficients involved in the updates of sparse diffusion LMS using the idea of message propagation. Moreover, we optimize the proposed coefficients with respect to mean-square-deviation at the steady-state. Simulation results demonstrate that the proposed method outperforms conventional methods in terms of the convergence performance.

The performance of packet processing applications is dependent on the memory access speed of network systems. Table lookup requires fast memory access and is one of the most common processes in various packet processing applications, which can be a dominant performance bottleneck. Therefore, in Network Function Virtualization (NFV)-aware environments, on-chip fast cache memories of a CPU of general-purpose hardware become critical to achieve high performance packet processing speeds of over tens of Gbps. Also, multiple types of applications and complex applications are executed in the same system simultaneously in carrier network systems, which require adequate cache memory capacities as well. In this paper, we propose a packet processing architecture that utilizes interleaved 3 Dimensional (3D)-stacked Dynamic Random Access Memory (DRAM) devices as off-chip Last Level Cache (LLC) in addition to several levels of dedicated cache memories of each CPU core. Entries of a lookup table are distributed in every bank and vault to utilize both bank interleaving and vault-level memory parallelism. Frequently accessed entries in 3D-stacked DRAM are also cached in on-chip dedicated cache memories of each CPU core. The evaluation results show that the proposed architecture reduces the memory access latency by 57%, and increases the throughput by 100% while reducing the blocking probability but about 10% compared to the architecture with shared on-chip LLC. These results indicate that 3D-stacked DRAM can be practical as off-chip LLC in parallel packet processing systems.

This paper expands our previously proposed semi-blind uplink interference suppression scheme for multicell multiuser massive MIMO systems to support multi modulus signals. The original proposal applies the channel state information (CSI) aided blind adaptive array (BAA) interference suppression after the beamspace preprocessing and the decision feedback channel estimation (DFCE). BAA is based on the constant modulus algorithm (CMA) which can fully exploit the degree of freedom (DoF) of massive antenna arrays to suppress both inter-user interference (IUI) and inter-cell interference (ICI). Its effectiveness has been verified under the extensive pilot contamination constraint. Unfortunately, CMA basically works well only for constant envelope signals such as QPSK and thus the proposed scheme should be expanded to cover QAM signals for more general use. This paper proposes to apply the multi modulus algorithm (MMA) and the minimum mean square error weight derivation based on data-aided sample matrix inversion (MMSE-SMI). It can successfully realize interference suppression even with the use of multi-level envelope signals such as 16QAM with satisfactorily outage probability performance below the fifth percentile.

Universal filtered multicarrier (UFMC) systems offer a flexibility of filtering sub-bands with arbitrary bandwidth to suppress out-of-band (OoB) emission, while keeping the orthogonality between subcarriers in one sub-band. Oscillator discrepancies between the transmitter and receiver induce carrier frequency offset (CFO) in practical systems. In this paper, we propose a novel CFO estimation method for UFMC systems that has very low computational complexity and can then be used in practical systems. In order to fully exploit the coherence bandwidth of the channel, the training symbols are designed to have several identical segments in the frequency domain. As a result, the integral part of CFO can be estimated by simply determining the correlation between received signal and the training symbol. Simulation results show that the proposed method can achieve almost the same performance as an existing method and even a better performance in channels that have small decay parameter values. The proposed method can also be used in other multicarrier systems, such as orthogonal frequency division multiplexing (OFDM).

Side-channel (SC) leakage from a cryptographic device chip is simulated as the dynamic current flowing out of the chip. When evaluating the simulated current, an evaluation by comparison with an actual measurement is essential; however, it is difficult to compare them directly. This is because a measured waveform is typically the output voltage of probe placed at the observation position outside the chip, and the actual dynamic current is modified by several transfer impedances. Therefore, in this paper, the probe voltage is converted into the dynamic current by using an EMC macro-model of a cryptographic device being evaluated. This paper shows that both the amplitude and the SC analysis (correlation power analysis and measurements to disclosure) results of the simulated dynamic current were evaluated appropriately by using the EMC macro-model. An evaluation confirms that the shape of the simulated current matches the measured one; moreover, the SC analysis results agreed with the measured ones well. On the basis of the results, it is confirmed that a register-transfer level (RTL) simulation of the dynamic current gives a reasonable estimation of SC traces.