Recently, there has been a demand for lead (Pb)-free solders for use in the electronics industry. However, this poses a challenge in their practical applications because the main component of typical Pb-free solders is tin (Sn) and therefore these solders are prone to oxidize easily. In this paper, we propose a novel technique for the reduction of oxides of the powder which is the raw material of Pb-free solders, and which has Sn as its main component using NH₃ decomposed species generated using a hot-wire (HW) method. It is confirmed that the tin oxide can be reduced by this treatment and the re-oxidation of the solder is also suppressed. Moreover, it is also confirmed that this treatment is effective in controlling the particle size of the Pb-free solder. Further, we clarify that the activation energy of the reduction of the tin oxide is almost zero by this process is almost zero, which indicates that the temperature dependence of the reduction is low.

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Recently high-density packaging technologies have been in strong demand in an effort to realize the ubiquitous networking society. A wafer-level chip size packaging (W-CSP) technology is one of the most promising technologies for high density and environmentally-friendly packaging. The purpose of this study is to propose a fabrication method for a multi-chip module system using W-CSP technology. In this study, we fabricated a two-chip module with W-CSP using an excimer laser to form via-holes and electro-plating to fill the via-holes. This study has two main new technologies: one is new via-hole formation using an excimer laser that makes small (30 μm diameter) and deep (50 and 100 μm) via-holes, with a micro-lens array used to shorten via-hole formation time. The micro-lens array makes one-line via-hole formation at once. The second new technology is new copper electroplating techniques to fill the via-holes which have same diameter (30 μm) and different depths (50 and 100 μm) by controlling additives and agitating conditions. In this study, we fabricated a two-chip module, and both chips were covered by resin simultaneously. The second chip, whose thickness was 50 μm, was mounted on a wafer (first chip) after the first chip had completed the wafer process. The second chip was thinned and mounted by die attachment film (DAF). Next, the mounted chips were spin-coater with polyimide or epoxy resin about 100 μm in thickness. Two types of via-hole with different depths, 50 and 100 μm, were formed by excimer laser to connect the wafer and mounted chip pads. Both types of via-hole had a diameter of about 30 μm. After via-hole formation, seed layers, sputtered Ti and Cu films, are necessary for subsequent copper electro-deposition. Using microscopy measurement, the seed layers were seen to be uniformly formed from the top to the bottom of the via-hole. Using a general mixture of additives, brightener, leveler, and suppressor, the via-holes were completely filled. By controlling the suppressor effect, the 100 μm deep via-holes were perfectly filled with the copper electroplating. Both mechanical agitation and current density are effective to ensure via-hole filling and optimization of these two factors is very important in filling via-holes. Moreover, an additional electroless copper seed layer to increase conductivity near the bottom of the via-hole is also effective to suppress voids there. Finally, the conductivities between the first and second chips were confirmed for the multi-chip module fabricated using W-CSP with excimer laser and copper electro-plating.

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The metallization of aluminum (Al), silicon nitride (SiN) and polyimide (PI) have been investigated by changing the activation method necessary to start electroless plating. The adhesion force between the substrate materials and the following electroless Ni–P plating film is investigated. A one-solution type activation method is too acidic for Al and a zincate process is necessary for metallization. The polyimide substrate showed enough adhesion force for tape peel test. The silicon nitride substrate is difficult to plate uniformly. To increase the adsorption of the Pd catalyst, a conditioning process is effective for the SiN substrate. For one-solution type activation, the zincate process is necessary for the Al substrate and the conditioning process is necessary for the SiN substrate. A two-solution type activation method is available for all substrates and three repetitions are necessary for the SiN substrate. The adhesion force between the plated film and substrates is quantified. The highest value was obtained for the Al substrate after the zincate process, and the lowest value was obtained for the SiN substrate after two-solution type activation. Sufficient adhesion force, over 600 kg/cm², was obtained for all substrates with the two-solution type activation method. Therefore, the two-solution method shows high potential for the metallization of wafers with various materials.

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The authors investigated shape-control technology for electronic devices using the material characteristics of solder. Specifically, the authors developed and put into practical use the following processes and structures: (1) A "Solder bump transfer process" for reducing variation in the solder bump heights. (2) A "Support ball structure", by which high-melting-point solder spacers are set on the four corners of a BGA to control the heights of solder balls. (3) A "Solder pouring process", which allows voidless soldering with molten solder poured into metallized parts on electronic devices. We found that the support ball method is effective for heavy BGA structure packages used in high-speed communication. A high-quality hermetic sealing package was realized by application of the solder pouring method.

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For aerospace applications, eutectic Sn–Pb solder has been used for soldered joints requiring high reliability. However, the use of lead-free electronic components has been spreading and such components have been required. For lead-free electronic components, electrode materials have been changed from Sn–Pb alloys to lead-free materials. In joints with eutectic Sn–Pb solder and Ni/Pd/Au electrodes, degradation of the mechanical properties of the solder due to the dissolution of Au and Pd into the solder is a concern. In this study, the effect of Au and Pd impurities on the tensile properties of eutectic Sn–Pb solder was examined.
In solders with Au ranging from 1 to 5 mass%, the tensile strength is stable at approximately 50 MPa, which is 1.25 times that of Sn–37Pb solder. Elongation decreases with increasing Au content. In solders with Pd ranging from 1 to 5 mass%, the tensile strength increases with increasing Pd content. Elongation decreases with increasing Pd content and is less than half that of Sn–37Pb solder. In the addition range investigated, Pd is more harmful than Au for elongation. In solders with both Au and Pd added, in the range less than 1 mass%, the tensile strength increases and elongation decreases with increasing contents of Au and Pd. It was clarified that the contents of Au and Pd should be less than 0.025 and 0.05 mass%, respectively, to prevent significant decrease in elongation.

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An erosion test was conducted to compare the erosion rates of SUS304 and SUS316 stainless steels by molten Sn–3Ag–0.5Cu (mass%) lead-free solder. Stainless steels attached with polyvinyl chloride were used to accelerate the occurrence of erosion by destruction of the passivity of stainless steel and to shorten the incubation period of the occurrence of erosion. The average erosion rate of SUS304 steel is approximately 20% faster than that of SUS316 steel, whereas the maximum erosion depth evaluated by extreme value analysis does not depend on steel type. From microstructural observation of erosion interfaces, it was found that Fe–Cr–Sn and Fe–Cr–Mo–Sn layers form at the erosion interfaces of SUS304 and SUS316 steels, respectively.

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Previously, the common understanding with traditional polymer-based thick-film flexible circuits is that their low circuit density with low electrical conductivity is because of an organic matrix in the conductor materials. The organic matrix does not allow any soldering for the polymer thick-film circuits. It is the major reason why thick-film circuits could not be the mainstream technology in the printed-circuit-board industry and semiconductor substrate industry even though the technology provides a much lower manufacturing cost and high productivity without wet chemical waste compared with traditional copper-etched circuits. However, advanced screen-printing processes using new conductive materials are making remarkable improvements to overcome the technical barriers, and are generating application opportunities as new electronic packaging technologies.

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The authors found inhibition of cracking in the interfacial Cu₆Sn₅ intermetallic when Ni containing Sn–0.7Cu alloy was used for soldering. It is thought that this crack inhibition occurred due to the stabilisation of the high temperature hexagonal Cu₆Sn₅ phase through the presence of Ni from a Sn–0.7Cu–0.05Ni solder alloy. To explore the mechanisms associated with the differences in joint integrity, in-situ synchrotron X-ray diffraction (XRD) at the Australian Synchrotron was conducted in the temperature range of 25 to 200°C. The results show that Ni stabilises a high-temperature allotrope of the Cu₆Sn₅ phase, avoiding stresses induced by a volumetric change that would otherwise occur on phase transformation.

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Copper deposited using bath additives added to the bath such as brighteners like Bis-(3-sulfopropyl)-disulfide (SPS) shows physical property changes when kept even at room temperature. In this research, the elements or groups contained in 2-Mercapto-5-benzimidazole (2M-5S), which have effects in preventing the property changes, are investigated. From this, Mercapto groups and Nitrogen atoms are thought to be essential and Benzene rings are thought to assist these effects. 2M-5S is thought to produce a strong union with the Cu(I) complex and coexisting additives using δ-polarized Nitrogen atoms and increases the amount of impurities incorporated into the deposits at the time of reduction.

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In this study, 60 solder compositions were examined in an effort to improve the integrity against impact loads of the solder joints on an electroless Ni–P/Au surface finish. The Ag, Cu, and Ni contents in the Sn-based solder varied from 0 to 4.5 wt%, 0 to 2.0 wt%, and 0 to 0.05 wt%, respectively. Impact shear tests were performed to investigate solder joint integrity after solder ball reflowing, after reflow soldering twice more, after storage at room temperature for 168 hours, and after storage at 150°C for 1,000 hours. According to the results, the Ag content should be as low as possible, the Cu content should be from 0.5 to 0.7 wt%, and the Ni content should be as high as possible. The Ag and Ni contents should be determined in consideration of the wettability and the board-level reliability of the solder joints.

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This paper describes the modelling analysis for a power-distribution network and demonstrates co-design and co-simulation in using the detailed prototype model, which includes a chip, package, and printed circuit board. A circuit simulator and a 2D solver using the finite element method are used to study the frequency and transient responses for the core switching noise. In the model, we assume a chip model (current profile and on-chip capacitance) and define the circuit parameters with an equivalent circuit to meet the target impedance. Then the physical design of the package and printed circuit board were done to check all of the required circuit parameters. According to the modelling and evaluation, the package design with a low equivalent series inductance capacitor in the bottom layer and a thin core structure is more advantageous than a capacitor in the top layer.

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Inkjet technology is believed to be suitable for the mask-less production of various electronic devices. Printed electronics using inkjet technologies have major benefits as shown below: 1) direct printing of metal patterns on large and/or flexible substrates is possible, 2) the waste of coating materials, which are usually expensive, is minimized. In this paper, the jetting characteristics of Ag nano particle dispersed ink with shear mode piezo print heads are described. A 2.7 pl droplet can be ejected with a minimum line width of 70 μm. For applications with flexible substrates, the inkjet patterning of electrodes for PCBs and thin film coating on PET substrates are described using a line-head module.

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Three types of inexpensive Pb-free solder joints, namely Zn-based and Bi-based solders, and a CuSn alloy were studied for application to the high-temperature operation of wide band-gap power semiconductor devices using GaN or SiC. Zn–Al solder sheets, whose melting point is 380°C were prepared, and then surface oxides were removed by RF plasma etching. Subsequently, Cu thin films were deposited by the DC sputtering method on the solder sheet. After that, joint samples were fabricated using a conventional electrical furnace with H₂/N₂ gas flow. That the joints were sufficiently dense was confirmed by scanning acoustic microscope. The wettability of the solder was improved due to contact between the pure Zn–Al solder without oxide and the Ni surface of the substrate, and the chemical reaction between the Zn–Al solder and the deposited Cu thin film. Bi with CuAlMn particle solders, whose melting point is 270°C, were fabricated and it was found that the solder has almost double the tensile strength of pure Bi. Excellent wettability was observed with the Ni or Pd thin film deposited on the Cu substrate. It was found that deposited Ni or Pd was not observed in the interface between the substrates after the joint samples were fabricated. CuSn alloy joints were fabricated using Sn thin films deposited and annealed on Cu substrates. The temperature during the annealing was kept at approximately 350°C; therefore, only the Sn film was melted and some chemical reaction occurred between the liquid Sn and solid Cu. Then, Cu₃Sn alloy, whose melting point is 640°C, appeared in the joint and the composition was confirmed by X-ray diffraction analysis. Furthermore, it was found that the CuSn alloy is harder than Cu as measured by nano indentation analysis. In addition, the joints showed excellent thermal cycle reliability.
Finally, the properties of these joints are summarized.

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With the continued shrinking of the system-in-package, there is increasing pressure to use double-sided flip-chip assembly to reduce the size of systems. The same thermal treatment used to assemble the flip-chip on one side is also done on the other side of the substrate. A concern is the low wettability of the solder when assembling the second flip-chip. The wettability of solder depends on the surface treatment of the pads of the substrate. Various surface treatments such as Organic Solderability Preservative (OSP), Electroless Sn plating (E-less Sn), and Direct Immersion Gold (DIG) are evaluated. OSPs with high solubility into flux showed good wettability with adequate margins. Even though E-less Sn showed good wettability, the margins were insufficient. Thin DIG showed poor wettability because the Au diffused into the Cu during the thermal treatments. Reliability tests were performed on the OSPs which showed good wettability. Good reliability was confirmed for the double-sided flip-chip packages.

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The mechanical and electrical reliabilities of fine bumps with diameters and heights on the order of scores of microns were studied, considering the growth of the intermetallic compound (IMC) at the interface between a tin bump and a copper thin-film interconnection. It was found that an increase in the thickness of the IMC changed the stress and strain fields around the interface significantly, and thus, changed the fracture mode from a fatigue crack of the solder to a fatigue crack of the copper interconnection or to delamination between the IMC and the copper interconnection. This is because the mechanical properties of the grown IMC differ from those of copper and tin and that a large number of Kirkendall voids appeared around the interface. In addition, the resistance of the bumps increased dramatically with the increment of the IMC layer because of the growth of the Kirkendall voids. Therefore, it is very important to minimize the growth of the IMC in order to assure the reliability of the bump joint structures.

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The effects of a third element, namely silver, copper, zinc, or antimony, on the microstructure and mechanical properties of eutectic tin-bismuth (Sn–Bi) solder were investigated. The investigation showed that, except for zinc, the addition of a trace amount of the third element improves the ductility of the Sn–Bi solder owing to the formation of a fine, homogeneous ternary eutectic microstructure. In particular, the antimony addition is the most effective in improving solder ductility. That is to say, the addition of 0.5 wt% antimony minimizes the grain size of the eutectic microstructure and increases the elongation up to about 40%. Moreover, an intermetallic compound, namely, SnSb, precipitated finely from the solid tin solution near the grain boundaries with bismuth. This fine precipitated intermetallic compound suppresses the coarsening of the eutectic structure and thus improves solder ductility.

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Three-dimensional molded interconnected devices (3D-MID) extend the range of classical printed circuit boards (PCB) to the third dimension. Electrical circuits can be routed over any surface forms. This enables innovative applications and new design possibilities. The combination of circuit carrier, housing, and further functions results in an increased density of integration with decreased process effort. One limitation of recent 3D-MID technologies is their incompatibility with modern area-array based electronic packages. Usually the high I/O count of such package types makes routing in only one electrical layer impossible and necessitates multilayer structures. To meet the future requirements of 3D-MID, a compatible fine-pitch multilayer process is developed. In combination with an established 3D-MID metallization process, it allows the flip-chip mounting of area-array packages. A sample device with three metallization layers is fabricated. The mechanical and electrical multilayer properties are investigated.

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The formation of Au microbump arrays for flip-chip bonding was investigated using an electroless Au plating bath. Generally, electroless Au deposition gives a low deposition rate, preventing the fabrication of Au bumps with heights of more than 5 μm. To overcome this problem, we developed a new electroless Au deposition process that employs a non-cyanide bath. This process delivers a high deposition rate, especially for fine bump patterns (bumps of less than 10 μm in diameter). Au bumps with a diameter and height of 10 μm each could be fabricated with a high deposition rate using the new electroless Au plating bath. Moreover, Au microbump arrays were successfully fabricated on Cu wiring. The practical feasibility of this technique was demonstrated by forming arrays with bump heights and bump diameters of 10 μm each and an array pitch of 30 μm. All film-formation processes were performed under cyanide-free conditions; thus, this process has a high industrial potential for fabricating ultra-fine Au microbump arrays.

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This paper describes the optimisation of the surface characteristics of a high-frequency substrate material widely used in the PCB (printed circuit board) industry by means of CF₄/O₂ plasma etching, in order to make it suitable for the fabrication of RF (radio frequency) circuit structures by a combination of inkjet printing and electroless plating. A statistical DoE (design of experiments) based on a CCRD (central composite rotatable design) was used to systematically vary the plasma etching parameters and explore the characteristics of the etching process. This experimental design yielded 31 substrates, all of which were assessed in terms of surface energy, surface roughness and adhesion. Out of these substrates, 5 were identified as having the most favourable surface characteristics. Finally, RF circuit structures in the form of S-band filters were fabricated on these substrates using an inkjet printing-electroless plating combination, and the RF performance of these structures was characterised and compared.

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Electrically conductive adhesives composed of a multi-functional epoxy-based matrix containing micro- and nano-fillers with bimodal and trimodal size distributions were prepared in order to investigate their electrical and thermal conductivities. When Ag flakes were used as the filler, anisotropy was clearly observed in the thermal conductivities due to the alignment of the flakes along the in-plane direction. A bimodal adhesive containing Ag flakes and spherical micro-particles exhibited a maximal value for thermal conductivity in the vertical direction when the content of the micro-particles was 50–60 wt% of the total filler loading, although its conductivity in the in-plane direction decreased monotonically with increasing content of micro-particles. With trimodal adhesives containing Ag flakes, micro- and nanoparticles, the Ag nanoparticles could be sintered during the curing process. Adequate dispersion and sufficient sintering of the nanoparticles were found to be essential in order to improve the electrical and thermal conductivities of these adhesives.

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There is a strong development activity constantly ongoing in the electronics packaging industry to find new and cost-effective packaging solutions. At the same time that existing package technology solutions are being pushed to the limit, completely new and revolutionary electronics manufacturing solutions are emerging to the market. A great challenge in the ongoing development is to be able to create a package technology solution that provides further miniaturization and improved electrical performance with a cost effective and robust manufacturing concept.
Imbera Electronics has developed several generations of Integrated Module Board (IMB) technology to embed discrete components inside an organic, low-cost PCB motherboard or substrate. The 1^st and 2^nd generations were initially developed in late 90's at the Helsinki University of Technology. The current focus is in the 3^rd generation IMB technology developed by Imbera Electronics in 2003. The 3^rd generation technology provides a flexible platform for multiple component types from low- to mid-range I/O count components.
In this paper the IMB technology concept is reviewed with a focus on technology capability, reliability, production quality and potential application areas. The cost impact of different production process alternatives are studied and reviewed. Also, an analysis of key cost drivers is presented.

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Previously, we developed a high-density assembly technology to miniaturize the motion control CPU SiP for humanoid robots. It is necessary to mount a number of passive components on an expensive buildup PWB to accomplish this CPU SiP assembly and satisfy electrical performance requirements. As a result, we developed an embedded device technology to realize further miniaturization and achieve excellent electrical performance with the CPU SiP. This paper is intended as an investigation of the impacts of module-level miniaturization with embedded active device technology on the electrical performance. From our investigation, it is concluded that the CPU-embedded SiP has excellent electrical performance, such as signal reflection, cross-talk noise and simultaneous switching output noise. In addition, the CPU-embedded SiP has sufficient signal transmission properties for a data rate of 4 Gbps. The results of this investigation will change the future technology position of module-level miniaturization with embedded device technology.

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A new type of low-temperature co-fired ceramic (LTCC) probes for high-frequency measurements fabricated using SiP technology is proposed. The advantage of this probe is that the metal tips for the electrodes can be made easily by cutting LTCC sheets during the fabrication process. A system with probe (SwP) consisting of a probe and a bandpass filter (BPF) is designed and fabricated. The frequency dependence of the reflection parameter S₁₁ and transmission parameter S₂₁ showed the good agreement between simulation and measurement. Also, the S-parameters of a SwP with a commercial discrete BPF are measured and compared to three types of BPF embedded SwPs. Finally, the near-end crosstalk (NEXT) and far-end crosstalk (FEXT) for a fabricated SwP array are investigated.

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In order to determine appropriate cooling solutions for 3D chip stacks in various cases, it is important to have a better understanding of the total thermal resistance of a 3D chip stack. For this purpose, precise thermal resistance measurements and modeling of each component of a 3D chip stack are important. The thermal resistance of interconnection is considered to be one of the thermal resistance bottlenecks of a 3D chip stack. In this study, a steady-state thermal resistance measurement method is employed for the thermal resistance measurement of interconnection. The thermal resistance of the 200 μm pitch C4's (Pb97Sn3) jointed samples are measured and the thermal conductivity of C4's is derived to be 18–24 W/mK. With regard to the thermal resistance of a silicon substrate, the thermal resistance of a silicon substrate with various interconnection pitches and diameters has already been modeled by considering the concentrated heat flow to interconnection, as presented in ICEP 2008.[15] Based on the modeled data, the thermal resistance reduction by underfill with various interconnection pitches and diameters is also studied.

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Three-dimensional (3D) integration is considered to be the most promising solution for the continuing improvement in device performance,[1] while the scaling of Si CMOS is approaching its economical and physical limits. Inter Chip Fill (ICF) resin, filled between the gaps of 3D stacked chips, is expected to improve the mechanical strength and corrosion resistance of such chips. Pre-applied resin, which is applied before the chip joining process, was evaluated for this application. The characteristics required for ICF materials are different from those for conventional flip chip underfills, because the ICF must fill much thinner, multiple gaps of the order of a few micrometers between the silicon dies for which there is no CTE mismatch.
In this paper, a new ICF resin was designed for the 3D chip stack. The polymerization and viscosity of the material at each joining process step were precisely optimized. As a result, we could confirm the applicability of pre-applied ICF materials to the 3D chip integration process joined by very low height solder bumps of an area array. We arrived at the idea of a novel Stack Joining process which could be effective to reduce chip stacking process costs and contribute significantly to higher reliability.

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