Characterization Method of Joints for Power Semiconductor Device Packaging

Abstract

We studied a method of characterizing joint materials such as solders and nanoparticles for use in semiconductor power device packaging. It is sometimes difficult to evaluate joint materials in actual packaging structures that use transistors/diodes, resin encapsulation and thick wire bonding because generally, deteriorations occur at multiple points in reliability tests. Simple structured samples consisting of a Si heater chip joined to a metal substrate were fabricated and their thermal properties were studied, including dependency on surface plating of the substrate, power cycle, thermal cycle and high-temperature reliability tests. The results verify that this method is suitable for evaluating the joint materials.