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The 24th JIEP Annual Meeting

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The 24th JIEP Annual Meeting

Trends of Enviromentally Friendly Technologies for Printed Wiring Board

Akihiko Happoya, Masamitsu Aoki, Akio Takahashi

Session ID: 10A-01
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_2

CONFERENCE PROCEEDINGS FREE ACCESS

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Recently there is a heightened concern about global environmental problems and safety to human body. As for electronic/electrical equipments as well, it is indispensable to deal with the environment, and environmental friendliness and safety of higher levels are increasingly required. In this report, we outline the trend of printed wiring boards positively achieving environmental friendliness while satisfying various required characteristics.

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Formation of Seed Layered Plating with High Adhesion for Epoxy Resin Substrate

Genki Kanamori, Shinya Tanaka, Mitsuhiro Watanabe, Hideo Honma

Session ID: 10A-02
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_6

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Development of alloying technique for printed metal pattern

Manabu Yoshida, Kouji Suemori, Sei Uemura, Satoshi Hoshino, Noriyuki T ...

Session ID: 10A-03
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_8

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We have developed and studied on materials for printable electronics.Printed electrodes having various work function are necessary for producing printable diode, printable EL device, and printable solar cell.In this paper, we will report a fabrication method of printed electrodes having various work function using our developed alloying technique.

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Study on Benzoxazine Resin Modified with Epoxy Resin

Mika Kagawa, Akio Takahashi, Toshiyuki Oyama

Session ID: 10A-04
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_10

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Decomposition process of β−ketocarboxylic acid silver sold ink and its wiring characteristics

Takahiro Kuwana, Mariko Htamura, Daisuke Wakuda, Katsuaki Suganuma

Session ID: 10A-05
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_12

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Development of pre-applied under fill for narrow pitch

Kazuhiro Nomura, Takuya Mizuno, Tomoki Isobe, Nobuo Ogura

Session ID: 10A-06
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_14

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Rapid curing silver paste

Kazutoshi Koshimizu, Akinobu Ono, Takayuki Imai, Shigeo Ota, Shinya Tn ...

Session ID: 10A-07
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_16

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Technology trends of high speed serial interface

Shusei Tago

Session ID: 10B-01
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_18

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Gbps Signal I/O of a Ceramic PGA Package with a Socket

Keitaro Yamagishi, Takuma Ishibashi, Soichiro Kametani, Tsuyoshi Kobay ...

Session ID: 10B-02
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_20

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Pin grid array packages with ceramic substrate is not used now for LSI with many pins because it has less pins than ball grid array package and can not be applied for high speed singals. We have analyzed and designed this type of package and socket to transmit several Gbps class signals between printed circuit board and LSI.

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About the examination of the board material for a super-high-speed transmission

Makoto Suwada

Session ID: 10B-03
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_22

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Study of influences of underfill material on millimeter-wave MMIC

Takashi Shimizu, Hiroshi Nakano, Ryosuke Suga, Yoshinori Kogami, Yasut ...

Session ID: 10B-04
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_24

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Study on Immunity Evaluation Method of Shielded Balanced Cable

Yusuke Suzuki, Satoshi Yoneda, Hideyuki Ohashi, Seiichi Saito, Naoto O ...

Session ID: 10B-05
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_26

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Calculation of Common-Mode Radiation from Multi-Channel Differential Signaling Transmission Line Based on Imbalance Difference Model

Tohru Matsushima, Tetsushi Watanabe, Yoshitaka Toyota, Ryuji Koga, Osa ...

Session ID: 10B-06
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_28

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The influence on skew within differential pair for 40GHz signal transmission

Takahide Nozaki, Hideyuki Nakanishi

Session ID: 10B-07
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_30

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The effect of circuit design on transmission characteristics at FPC

Norifumi Sasaoka

Session ID: 10B-08
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_32

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We made so many kinds of our original FPC(Microstrip-Line,Strip-Line) in changing various factors. Changing factors are shape of GND pattern, width of signal pattern, thickness of copper, thickness of resin.We publish the effect of circuit design on transmission characteristics at FPC from data of Characteristic Impedance and S-parameter.

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Analysis model's optimization by DCAM'START'

kazuyuki saito

Session ID: 10B-09
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_34

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Mechanism for Spontaneous Zinc Whisker Growth from an Electroplated Zinc Coating

Alongheng Baated, Keun-Soo Kim, Katsuaki Suganuma

Session ID: 10C-01
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_36

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Micro-texture dependence of migration resistance of electroplated copper interconnextions

Naoki Saito, Naokazu Murata, Kinji Tamakawa, Ken Suzuki, Hideo Miura

Session ID: 10C-02
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_38

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Both electromigration and stress-induced migration resistances of electroplated copper thin film interconnections were discussed experimentally. It was found that the micro texture of the interconnections varied dramatically from fine columnar grains to large polycrystalline grains depending on the conditions of electroplating and annealing. The migration resistances also changed drastically depending on the micro texture. It was also found that sulfur atoms degrades the stress-induced migration resistance significantly.

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Effect of mechanical properties of underfill material on the local deformation of a silicon chip mounted on area-arrayed fine bumps

Kohta Nakahira, Hiroki Kishi, Ken Suzuki, Hideo Miura

Session ID: 10C-03
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_40

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Local deformation of silicon chips mounted on area-arrayed fine metallic bumps has increased drastically in mobile application because of the thinning of the chips. Since such local deformation increases the amplitude of the local residual stress in the chips, the reliability of the chips is degraded seriously. In this study, the effect of the mechanical properties of underfill material on the local deformation was measured by using stress-sensing chips. It was found that the dominant factors of the local deformation changed drastically as a function of the bump pitch.

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Observation of the Reaction of Tin on Stainless steel Surface by AES

Youhei Sejimo, Yosiharu Kariya, Takasi Kimura

Session ID: 10C-04
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_42

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Study on capacitance type minute printed wiring board inspection system

Masanori NOGUCHI, Yukio SAITO, Okitoshi TSUNODA

Session ID: 10C-05
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_44

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Evaluation Method of Various Electrical Characters using PWB Coupon

Hideki Mizushina, Masataka Hirokawa, Jun Kamiya, Satoru Haga

Session ID: 10C-06
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_46

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Built-in Test Circuit for Interconnect Open Tests

Masaki Hashizume, Kenichi Uchikura, Akira Ono, Hiroyuki Yotsuyanagi, M ...

Session ID: 10C-07
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_48

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We propose a built-in test circuit for testing opens that occur at interconnects between ICs and a test method with it in this paper. Also, test input vectors for tests using the test circuit are proposed that will be provided with a boundary scan mechanism. Furthermore, we show that opens at interconnects between ICs can be detected with the test circuit by Spice simulation.

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Detection of height of minute balls based on triangulation using detected 2-D images

Yasuhiko Hara, Narihiro Kawada, Kenji Shirai, Yoshikazu Kobayashi, Hid ...

Session ID: 10C-08
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_50

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Domestic and international standards of device embedded boards

Akikazu Shibata

Session ID: 11A-01
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_52

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The technology has been developed now including Japan, Europe and Korea. JPCA developed a JPCA standard based on the ePADs group activities of JIEP as JPCA EB-01 1Ed in June 2008 and was revised by JIEP and JPCA to 2nd Ed. and published in June 2009. The document was reported at meetings of IEC and IPC. JPCA EB-01, 2nd Ed. was proposed to IEC/TC91 in October 2009 as a PAS and approved is now an official international document. An effort is being made in Korea and they are proposing a document on electrical measurement of device embedded boards.

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Cu Core Printed Circuit Board with Embedded Passive and Active Devices

masashi miyazaki

Session ID: 11A-02
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_56

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The coming generations of portable products require the miniaturization, the demand for higher density of functions, and increasing signal frequencies. In order to satisfy these requirements, we have developed new hardware technology of module products called EOMIN (Embedded Organic Module Involved Nanotechnology).This paper describes the performance of small DCDC converter module which made by EOMIN. FEM simulations of thermal performance of embedded chip and connection reliability to embedded components will be presented.

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Fine-pad-pitch Fanning-out embedded LSI Package using Cu Base Plate

Hideya Murai, Kentaro Mori, Masaya Kawano, Shintaro Yamamichi

Session ID: 11A-04
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_60

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The Latest Trends of Embedded Passive & Active Devices

Susumu Honda

Session ID: 11A-03
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_62

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Embedded active and passive technology for interposer and main board has been advancing rapidly for ultra-small size and high performance electronic products. Nowadays, the Si interposer by approaching interposer wiring to IC chip global wiring has been resulting to the convergence of IC chip and interposer. Ultra-thin chip components and Si-based IPDs are also being produced for the embedded passive components. These new trends and main targets will be presented.

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Analysis of bonding part of gold stud bump in bare die embedding substrate

Katsumi Miyama, Hiroyuki Tanaka

Session ID: 11A-05
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_66

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Wideband Ultralow Impedance Evaluation of Power Distribution Network for Decoupling Capacitor Embedded Interposers

Katsuya Kikuchi, Koichi Takemura, Chihiro Ueda, Osamu Shimada, Toshio ...

Session ID: 11A-06
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_68

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Impedance properties of SrTiO3 Thin Film Capacitors on Si Interposers for 3D Integration

Koichi Takemura, Katsuya Kikuchi, Chihiro Ueda, Kazuhiro Baba, Masahir ...

Session ID: 11A-07
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_70

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Fabrication of High Capacitance Interposer Substrate

Tomokazu Tanase, Hiroshi Nakano, Satoru Amou, Haruo Akahoshi, Yoshitak ...

Session ID: 11A-08
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_72

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Acid Copper Plating for Flat Top Surface in SAP

Akinobu Ohno, Tetsuro Eda

Session ID: 11A-09
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_74

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Investigation of electroless copper plating for low profile surface in SAP

Satoru Shimizu, Aya Iwakiri

Session ID: 11A-10
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_76

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Effect of Diallylamine System Additives for Copper Via Filling

Hideyuki Kuri, Naoki Okamoto, Takeyasu Saito, Kazuo Kondo, Masaru Buny ...

Session ID: 11A-11
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_78

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Plating Growth Mechanism of Via-filling

Yohei Wakuda, Masaharu Sugimoto, Mitsuhiro Watanabe, Hideo Honma

Session ID: 11A-12
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_80

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Investigation of Copper Filling Using Copper Sulfate bath

Masaki Kobayashi, Takaaki Maruyama, Masaharu Sugimoto, Hiroaki Kouzai, ...

Session ID: 11A-13
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_82

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Evaluation of Catalyzing Method using Copper for Electroless Plating

Tomohito KATO, Kunihito BABA, Mitsuhiro WATANABE, Hideo HONMA

Session ID: 11A-14
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_84

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The investigation for the improvement on the strength of electrodeposited copper for circuit materials

Mitsuyoshi Matsuda, Takuya Takahashi, Sachio Yoshihara, Makoto Dobashi

Session ID: 11A-15
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_86

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Influence of Acid Copper Plating Additive for Pulse Periodic Reverse

Yuka Iwamoto, Shingo Nishiki, Takashi Matsunami

Session ID: 11A-16
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_88

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Plating on smooth epoxy resin using atmospheric UV treatment

Tatsuma Kaneda, Masaharu Sugimoto, Katsuhiko Tashiro, Mitsuhiro Watana ...

Session ID: 11A-17
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_90

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Metallizing of Cyclo Olefin Polymer Film Treated by UV Irradiation

Yoshiyuki Nishimura, Sayaka Arashiro, Kunihito Baba, Mitsuhiro Watanab ...

Session ID: 11A-18
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_92

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Low dielectric material has been commonly used as a printed circuit board substrate to reduce the dielectric loss. PTFE is one of the candidates for such a Low-k material. Conventionally, a complicated etched surface has to be created by a strong etching media in order to achieve a good adhesion between the deposited metal and substrate. However, this complicated etched surface becomes a problem due to the transmission loss through the skin effect. Therefore, we focused on the applicability of a Cyclo Olefin Polymer (COP) that has an electric characteristic equal to PTFE.

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Impact of Molecular Interface on Copper after Epoxy Lamination and HAST testing

Werner Kuhr, Steven Shi, Craig Rhodine, Shigeo Nakamura, Yoichi Kubota

Session ID: 11A-19
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_94

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To achieve a good adhesion b/w smooth Cu circuit and insulation in multilayer PWB, we have developed a molecular interface layer that provides adhesion without roughening the Cu. The Cu surface is modified with a molecular reagent that promotes adhesion to the subsequently applied dielectric layer, using a reaction to functionalize Cu and provide adhesion sites in a single step. This simplifies the treatment process and provides significant cost savings. Examination of the treated surfaces with peel test and cross section after reflow and HAST shows the robustness of the new process.

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Dry film resist for chemical milling

Shinichi Kunimatsu

Session ID: 11A-20
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_96

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A Stripline Filter for 60GHz Band with PCB Using Graft Polymer

Kenichi Shirota, Hok Huor Ou, Seiji Nishi

Session ID: 11A-21
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_98

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Generally, A bandpass filter for 60GHz band is designed by using waveguide, A bandpass filter designed by strip line structure, easily fine pitch design, with PCB using low dielectric constant and low loss material (Graft Polymer).As a result, a bandpass filter, good characteristics and good consistency with simulation, was proposed.Also it will be expected to enable low cost and fine pitch design of millimeter wave circuits and to be useful for WiGig applications.

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Regulation of Radiated Emission above 1 GHz

Chiharu Miyazaki

Session ID: 11B-01
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_100

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The regulation for radiated emission from information technology equipments above 1 GHz is provided by CISPR 22 (Ed. 5, Amd. 1, 2005). This regulation has been scheduled to the beginning of mission in start Japan and Europe since 2010. This paper shows the limits for the radiation emission (CISPR 22, Ed. 5, Amd. 1,2005), the measuring instruments (CISPR 16-1-1, Ed. 2, Amd. 1, 2006), the measurement methods (CISPR 16-2-3, Ed. 2, 2006) and the measurement site evaluation methods (CISPR 16-1-4, Ed. 2, 2007).

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Evaluation of EMI by high speed signal operational mode

Toshiyuki Kaneko

Session ID: 11B-02
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_102

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A Fundamental Study for Near-Field Location Estimation of Electromagnetic Sources Using MUSIC Method and Its Application to EMC Measurements.

Akio Fukuda, Kohji Koshiji

Session ID: 11B-03
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_104

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Study on wireless power and data transmission system for mobile electronic devices

Yagi Akira, Kohji Koshiji

Session ID: 11B-04
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_106

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Analysis of efficient electric power transmission between antenna loops

Hodeo Kikuchi

Session ID: 11B-05
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_108

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