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In this paper, a technique to analyze the multilayered power distribution networks efficiently is proposed. The Block-LIM, which can perform the high-speed simulation of the network including the mutual coupling circuit elements, has been proposed. However, the Block-LIM has the restriction on the time step size by the reason why the Block-LIM is the explicit technique. In the proposed approach, the restriction is relaxed by applying the alternating direction implicit method to the Block-LIM. From the numerical results, the efficiency of the proposed approach is confirmed.

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In this paper, we propose an iterative latency insertion method (LIM) for a fast transient analysis of large linear networks. Although the basic LIM is much faster than conventional SPICE-like simulators, a time step size used in a simulation is strictly limited by a stability condition. In the proposed method, we can successfully relax the limitation by using iterative updating formulas. A numerical stability and accuracy of the iterative LIM are also estimated, and some numerical results show that the proposed method can perform a faster simulation than the basic LIM.

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The national projects on 3D integration technologies have been running in Fukuoka since 2002. Three dimensional SiP design tool,TEG chips for evaluation of assembling process, several evaluation equipment such as SELBIC have been developed so far. In next April, a new research institute will be open in Itoshima, Fukuoka. The main research area is 3D integration technologies, mainly the device embedded substrate.

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A 3-dimensional clustering placement algorithm is suggested for the placement of components in printed wiring board (PWB). The placement of clusters, each of the clusters are placed by dividing the 3-dimensional space of PWB in the horizontal and vertical directions alternatively. In this talk, the evaluation results and the new problems are reported.

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Simulation technology of package substrates and mother boards is getting more and more mature each year. However, in order to effectively use a simulation technique, it is very important to have a proper understanding and careful selection of model, algorithm and parameters. In this paper, we focus on the assembly pads of a substrate, and report the results of our study.

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Simulation by using IBIS model become essential to the design forhigh-speed transmission line such as memory bus but there are morethan few cases which is using IBIS model without deep understanding ofdescriptive content of it. For example, the non monotoniccharacteristic issue is modified automatically by several kind oftoday's simulators but usually we can not see the impact of contentsof modification on the signal integrity simulation's result.In this paper, we research that's influential point and report theresults of our study.

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The design of the PWB which is sued for very high frequency signal, it is important to control the characteristics impedance of the etch.It is difficult to match the inpedance of the via and the footprint of the components. I designed the PWB for handle the over 10 GBPS signal by using 3D electromagnetic anasysis.

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A new series of liquid crystalline epoxy monomers were prepared forhigh thermal conducting thermosets. The liquid crystalline epoxymonomers were cured with diamines and the resulting self-assembledstructures were characterized by using differential scanningcalorimetry (DSC), polarized optical microscope (POM) and wide angleX-ray scattering (WAXS). The thermal conductivity was investigated.

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Generally, a micro-patterned phlythiophenes is fabricated by a microcontact printing method. However, this method requires complicated operation resulting in low productivity. To overcome this problem, direct patterning on polythiophenes based on photolithographic method is highly required. In this work, the new negative-type photosensitive polythiophenes consisting of poly(3-hexylthiophene), a cross-linker and a photoacid generator have been developed.

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Although there are a lot of the challenges of 3D-IC development, we are focusing on the die to die interconnection with ultra fine pitch and the underfill material development between die to die. As for the die to die interconnection, IMC bonding that is the small solder volume connection was developed. On the other hand, the the epoxy resin between 3D chips is different from the 2D, and very high thermal conductivity is needed. Therefore, the epoxy resin is coated on Wafer with bumps and then the solder joints and underfill are formed simultaneously.

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The solitary electromagnetic wave (SEMW) theory is being optimized to the switching mode circuit including the digital circuit, and it is faithful to the physics including electromagnetism and is dominant on the power lines and signal lines. It makes easy the analysis of the signal formation, signal integrity (SI), skew, power bounce, crosstalk, EMI, and immunity. The on-chip low impedance lossy line (LILL) technology is effective for the SI, the skew, the power bounce, EMI, and the immunity. The matched impedance lossy line (MILL) technology is effective for the SI and crosstalk.

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HSPICE(tm) compatibility simulator have some W-element models for transmission line analysis. These models are old style RLGCmodel, or Tablmodel that can support tabulated frequency samples data. It is important to consider the “causality” of W-element for time domain simulation. This paper present some examples for Causal and Non-Causal model simulation.

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The human channel communication was applied to the user interface to detect the approaching direction of human arm. Its feasibility was shwon by computer simulation.

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A transceiver with impulse raido scheme has been developed for on-body communication. Its performance has been evaluated experimentally and its feassibility has been confirmed.

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The needs for understanding behaviors of electromagnetic noise due to electrostatic discharge (ESD) at the design stage of an electronic system and taking adequate countermeasures are recently increasing. Since the ESD noise is strongly influenced by printed circuit board (PCB) and chassis, numerical simulations are necessary to quantitatively understand its behavior. In this work, we consider grounding methods for metal chassis and PCB as a typical countermeasure against the ESD noise and demonstrate FDTD simulations of transient ESD behaviors for some grounding locations.

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Recently, the application field of a high-speed differentialtransmission system has expanded, it is important to understand thenoise immunity of the twisted pair cable. The shielded twisted paircable (STP cable) is used for increase of the noise immunity of thetwisted pair cable, but we must consider the terminal treatment of theshielding sheath in STP cable. In this report,we studied the noiseimmunity to the terminal treatment of the shielding sheath in STP cable.

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A Research Group of "Embedded Passive Active Devices", EPADs in JIEP has investigated embedded technology for printed wiring board and the EPADs have cooperated the standardization with JPCA. The standardization is purposed to be world wide standardization and new WG6 is established for embedded technology. This presentation foucused on recent activity of standardization.

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