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The 24th JIEP Annual Meeting

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The 24th JIEP Annual Meeting

Thermal design for optical transceivers by Computational Fluid Dynamics

hiroshi kawamura, kazushige oki, hiromi kurashima

Session ID: 11B-06
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_110

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Simulation Study on Deformation of Soldering Process

Yasushi Yamada, Tsuguo Kondoh, Toshihiko Kikuchi, Hirofumi Hoshina, Ka ...

Session ID: 11B-07
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_112

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Historical Perspective on Power Integrity in Electronics

Kanji Otsuka, Yutaka Akiyama

Session ID: 11B-08
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_114

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Gradually power integrity for digital circuits is recognized strongly to be important. However, this is not new problem which has been discussing since 1960s. I will try to search the history, and to analyze the technical change for the time span. Consequent the perspective will be made to ideal direction.

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Power Integrity with Chip equivalent circuit

Atsushi Tomishima, Motochika Okano, Toshiyuki Kaneko

Session ID: 11B-09
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_116

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An evaluation of the immunity characteristics of an LSI embedding capacitors in an interposer

chie sasaki, yoshiyuki saito, eiji takahashi, yasuhiro sugaya, hideki ...

Session ID: 11B-10
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_118

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The study of EMI radiation by PCB power plane structure

Chihiro Ueda, Kanji Otsuka

Session ID: 11B-11
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_120

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Unnecessary noise radiation of a low frequency band decreases by using the stacked pair power plane structure from the PCB conventional power plane structure. The characteristic of stacked pair structure is considered from simulation data and actual measurement data.

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Calculations and measurements of propagation constant of a microstrip line

Ryohei Yoshitomi, Yoshio Kobayashi, Zhewang Ma

Session ID: 11B-12
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_122

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Coupling Characteristics of Composite Right and Left Handed Transmission Line

Katsumata Masaki, Koshiji kohji

Session ID: 11B-13
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_124

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Microwave Measurements of Complex Permittivity of High Loss Dielectric Rods Using a Multi-Mode TM0m0 Cavity

Shogo Kaneko, Yoshio Kobayashi, Ma Zhewang

Session ID: 11B-14
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_126

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Discussions for Measurement Precision of Complex Permittivity in Tangential Direction of a Dielectric Substrate by a Multi-Mode TE 0m1 Circular Cavity

Yoshio Kobayashi, S. M. Nazarat Hossain, Zhewang Ma

Session ID: 11B-15
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_128

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Microwave and Millimeterwave Characteristic Mearsurments of Cyclo Olefine Polymer Substrate

Shuhei Wadayama, Yoshio Kobayashi, Zhewang Ma

Session ID: 11B-16
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_130

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DPA Characteristic Measurement for Simulation-based Side-Channel Analysis

Toshihiro Katashita, Akashi Satoh, Katsuya Kikuchi, Hiroshi Nakagawa, ...

Session ID: 11B-17
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_132

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Calculation of Return current on incomplete Ground plane

Tatsuya Sakai, Takashi Sakusabe, Takehiro Takahashi, Noboru Schibuya

Session ID: 11B-18
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_134

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Study on low-impedance power distribution network in multilayer printed circuit boards

Kazunori Futamura, Takahiro Yagi, Satoru Haga

Session ID: 11B-19
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_136

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With low voltage and high current of Electronic Devices in recent years, gain importance for stabilization of power supply plane.This paper conducted a simulation study of structural about low impedance of the power planes in multilayer printed circuit board.

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Influence of decoupling device on common-mode current distribution

Kazuya Kumehara, Koichiro Masuda, Kohji Koshiji

Session ID: 11B-20
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_138

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Method of high frequency noise reduction for power delivery system in the PCB

Hiroyuki Motoki, Hideyuki Nakanishi

Session ID: 11B-21
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_140

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Modeling Analysis and Evaluation for Switching Voltage Regulator

Narimasa Takahashi, Yoshiyuki Kosaka

Session ID: 11B-22
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_142

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According to CPU tendency to be high performance, low voltage and large current, optimizing the circuit design and the packaging design is one of the important items in switching power supply system. In this paper, the DC-DC converter substrate that applied the simulation was made and was compared with the measurement result. As the result, it was confirmed that the simulation results about output waveform and radiated noise have correlated with measurement results.

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A Verification of the Design Method for Intra Electromagnetic Compatibility Problem via an Antenna

Tomoya Maekawa, Hideki Iwaki, Toru Yamada, Koichi Ogawa

Session ID: 11B-23
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_144

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Recently, the noise generated from digital circuits leaks into the receiver circuit via an antenna,and this makes the receiver sensitivity deteriorate. To solve this problem, we have developed a novel design method according to the correlation between the magnetic distributions of antenna and noise source, evaluated the validity of the proposal method using the TEG imitating portable telephone. Then, we clarified that a good correlation between the product of the two magnetic distribution and receiving noise can be obtained.

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Development of Composites Sheet using Epoxy Resin with Mesogen Molecular Groups

Tomoo Nishiyama, Hiroyuki Takahashi, Hideyuki Katagi, Naoki Hara, yosh ...

Session ID: 11C-01
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_146

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Study of Low CTE Technology to Reduce Warpage of FC-BGA

Yoshihiro Nakamura, Kasumi Ikeba, Masaaki Takekoshi, Shinji Tsuchikawa ...

Session ID: 11C-02
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_148

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Photosensitive Semi-alicyclic Polyimide with Low Coefficient of Thermal Expansion

Tomohito OGURA, Tomoya HIGASHIHARA, Mitsuru UEDA

Session ID: 11C-03
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_150

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Development of Ultrathin and Low-CTE Fabric consist of Organic Fiber

Kentaro Uesugi, Shinji Yoshikawa, Yoshinori Gondoh, Yashuyuki Kimura

Session ID: 11C-04
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_152

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Development of Thermal Conductive Thermoplastic Polyimide

Kenji Iida, Akira Sannomiya, Kotaro Asahina

Session ID: 11C-05
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_154

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Nowadays, thermal interface materials(TIM) are necessary for the LED devices and the power devices because the power of these devices are becoming higher and higher. So we developed "Thermal Conductive Thermoplastic Polyimide",which has high thermal conductivity (5.0W/mK), insulation and adhesive ability, to meet these needs. This new material can complete the bonding process less than 1 hour (The long time curing process isn't necessary!). We will present about the other features of this material in detail.

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Thermal Conductivity of Epoxy/BN Composites Controlled by Liquid Crystalline Structure

Miyuki Harada, Nana Hamaura, Mitsuazu Ochi

Session ID: 11C-06
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_156

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Build-up insulator material with low dielectric tangent and low CTE

Takayuki Kobayashi, Toshiaki Tanaka, Isao Suzuki

Session ID: 11C-07
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_158

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Present conditions and perspective of in-vehicle electronics packaging

toshihiro miyake

Session ID: 11C-08
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_160

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From the trend of a control system for cars, I spoke the electronics packaging technology which will become more and more important in future. I spoke necessity of each “small high density packaging” and “the packaging for large electric current” and some examples for “systematization” and “the being electromotive”.

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Solidification Process After Growth of Primary Ag₃Sn in Sn-Ag-Cu Alloys

Yoshiko Takamatsu, Hisao Esaka, kei Shinozuka

Session ID: 11C-09
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_164

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Thermal Fatigue Reliability Studies of Sn-Ag-Cu-Ni BGA Solder Joints on Electroless Ni-P/Au Surface Finish

Fumiyoshi Kawashiro, Masaaki Yoshikawa, Hisayuki Tsuruta, Takaki Etou, ...

Session ID: 11C-10
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_166

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Influence of print shape on the solder paste wettability test

Kenichi Yamamoto

Session ID: 11C-11
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_168

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Application of Laser Process for Semiconductor Packaging Technology

Takao Nogi, Hajime Takagi, Tomoyuki Kitani, Kentaro Suga, Akira Tojo, ...

Session ID: 11C-12
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_170

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Multi-chip Module Fabricated by W-CSP Using Excimer Laser Via-hole Formation and Cu Electroplating

Ichiro Koiwa, Takashi Suzuki, Toshio Tamura, Kentaro Koiwa, Yohei Waku ...

Session ID: 11C-13
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_172

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Evaluation of Junction Structure for Novel Wafer Level Packaging Technology Using Laminating Process

Yasuyuki Yanase, Mayumi Nakasato, Kouichi Saito, Hajime Kobayashi, Ats ...

Session ID: 11C-14
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_174

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Development of CdTe-ASIC hybrid for X-ray Flat Panel detector

Yoshio Mito, Tatsuhiro Koizumi, Tooru Kina

Session ID: 11C-15
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_176

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The 4-sides buttable CdTe-ASIC hybrid module for X-ray Flat Panel Detector(FPD) has been developed by applying Through Silicon Via(TSV) technology to the readout ASIC.The ASIC has 128x256 channels of charge integration type readout circuit having the area of 12.9x25.7mm. The CdTe sensor of 1mm thickness, having the same area and pixel of 100um pitch, was fabricated from the Cl-doped CdTe single crystal grown by Traveling Heater Method(THM).Then the CdTe pixel sensor was hybridized with the ASIC using the bump-bonding technology.We will introduce these technologies.

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Thermal Performance of a Thermally Enhanced Package Using Thermally Conductive Die Bonding Materials

Nae Yoneda, Kenya Kawano, Kazuhiko Yamada, Hiroki Hayashi

Session ID: 11C-16
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_178

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We measured and simulated the thermal performance of small-sized thermally enhanced packages which constructed with several type of die bonding materials with different thermal conductivity range of 2 to 80W/m/K. As a result, as for steady-state thermal resistance does not almost depend of the thermal conductivity of adhesive. On the other hand, thermal conductivity of the adhesive and gluing area ratio of the adhesive has significantly influence on the transient temperature rise with instantaneous large heat dissipation.

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Study on Improvement of Inequality in Surface Activated Bonding

Masato Taira, Yuinghui Wang, Jian Lu, Eiji Higurashi, Tadatomo Suga

Session ID: 11C-17
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_180

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Surface Activated Bonding of Au-substrate and Vertical Aligned Multi-walled Nanotubes

Masahisa Fujino, Tadatomo Suga, Ikuo Soga, Daiyu Kondo, Yoshikatu Ishi ...

Session ID: 11C-18
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_182

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FPC on Board Technology Utilizing Solder Particles Containing Resin Paste

Hiroki Maruo, Koji Motomura, Hideki Eifuku, Tadahiko Sakai

Session ID: 11C-19
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_184

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The study on bonding process of FCBGA

Satoshi Amari, Masao Oshima, Fumihiko Taniguchi, Ken Shono, Takashi Su ...

Session ID: 11C-20
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_186

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Bridge Connection Behavior in "Chemical Flip-chip Bonding" Process

Yasuhiro Yamaji, Tokihiko Yokoshima, Noboru Igawa, Katsuya Kikuchi, Hi ...

Session ID: 11C-21
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_188

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To overcome mechanical problems associated with the downsizing of theinterconnect bumps for flip-chip bonding, we have proposed a method of"Chemical Flip-chip Bonding" by employing chemical deposition. In thisstudy the correlation between bridge phenomenon and diffusion of thereaction products generated from surfaces of facing pads was experimentallydemonstrated using the original test chips with various pad-to-padconfigurations. The results also confirmed that this method is effectivefor long pad-to-pad connection with the distance of more than 50um.

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Evaluation of three dimensional thermal deformation during reflow process by using digital image correlation method

Yasuyuki Takanashi, Kenichi Ikeda, Shunsuke Kanetsuki, Shunji Araki, S ...

Session ID: 12A-01
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_190

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Improvement in fall joint reliability of CSP with partial reinforcement resin

Koji Motomura, Seiichi Yoshinaga, Yoshiyuki Wada, Tadahiko Sakai, Shoj ...

Session ID: 12A-02
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_192

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Highly Acceleration Life Test of Solder Joint under Low Temperature

Masaru Morita, Nobuyuki Hayashi, Teru Nakanishi, Katsusada Motoyoshi, ...

Session ID: 12A-03
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_194

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Efficiency Improvement of Solder Joint Fatigue Life evaluation for a High-end Pb-Free Glass Ceramic BGA Package.

Kenji Fukuzono, Masateru Koide, Manabu Watanabe

Session ID: 12A-04
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_196

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Packaging Technology Required by SiC Devices

Hiroshi Yamaguchi

Session ID: 12A-05
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_198

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The expectations of SiC power devices are increasing in the field of power electronics. SiC power devices have many excellent characteristics compared to those of Si power devices, however, high level packaging technology are required in order to make full use of SiC devices. From this viewpoint, the expectations of packaging and wiring technology are pointed out.

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Creep-Fatigue Life Evaluation for Sn-3.0Ag-0.5Cu Solder

Shengde Zhang, Masao Sakane

Session ID: 12A-06
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_200

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Fatigue Failure Prediction of Solder Joints using Accumulated Damage Model

Takeshi Terasaki, Hisashi Tanie, Nobuhiko Chiwata, Motoki Wakano, Masa ...

Session ID: 12A-07
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_202

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The Overview of Electrical Vehicle Technology and Its Possibility

Kenji Tanaka

Session ID: 12A-08
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_204

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Preparation of biomimetic silicon surfaces using self-organized porous polymer films as novel dry etching masks

Yuji Hirai, Hirotaka Nakamichi, Hiroshi Yabu, Yasutaka Matsuo, Kunihar ...

Session ID: 12A-09
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_206

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Effect of joining process on bondability of joints using Cu nanoparticle paste

Tomoaki Hirano, Hiroshi Nishikawa, Tadashi Takemoto, Nobuto Terada

Session ID: 12A-10
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_208

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Bonding Technique Using Micro-Scaled Silver-Oxide Particle for In-situ Alloying of Silver and Copper

Eiichi Ide, Toshiaki Morita, yuji Kawauchi

Session ID: 12A-11
Published: 2010
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.24.0_210

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