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The 18th JIEP Annual Meeting

Displaying 1-50 of 122 articles from this issue

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High Speed Pick-up Technology for Thi n Semiconductor Chips

hiroshi honma, noriyuki oroku, kosuke inoue, hitoshi odashima, chuichi ...

Session ID: 17A-01
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.1.0

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Room Temperature Silicon Direct Bonding Using Sequential Activation Process

Tae Hyun Kim, Howlader M.M.R., Suga T.

Session ID: 17-A02
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.3.0

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Room temperature silicon direct bonding was obtained by sequential activation process consisting of oxygen plasma and nitrogen radical activation methods. Bonding interface is as strong as silicon bulk at room temperature.

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Application of ultra fine grained diamond film

Yasushi Matsumoto, Katsunori Tomari, Katsuo Kazahaya, Toshio Fukunisi

Session ID: 17A-03
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.5.0

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Development of Novel Adhesive Films for Protecting Backside of Flip Chips.

tomonori shinoda, takashi sugino, osamu yamazaki

Session ID: 17A-04
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.7.0

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Effects of residual silicone in dicing tapes on packaging semiconductors

akinori sato, Koichi Nagamoto, Katsuyoshi Matsuura, Kazuhiro Takahashi ...

Session ID: 17A-05
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.9.0

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The evaluation of dependence on electroless plating conditions for fine-pitch copper conductor lines in a nano-porous substrate utilized photo-induced selective plating method

Kou Yamada, Hiroshi Yamada, Toshiro Hiraoka, Yasuyuki Hotsuta, Shigeru ...

Session ID: 17A-06
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.11.0

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We have realized fine-pitch Cu conductor lines in a nano-porous substrate utilizing photo-induced selective plating method which includes the growth of fine Cu particles and its electroless plating. The evaluations of fine pitch Cu conductor lines were performed by the observations of the Cu conductor line shape and the Cu filling ratio while changing several conditions of Cu electroless plating. As a result, it was found that the electroless Cu plating behavior in the nano-porous structure and the optimum electroless plating conditions into the nano-porous substrate.

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Short term evaluation method for whisker growth

Munehisa Kishimoto, Masato Nakamura, Hiroki Morii

Session ID: 17A-07
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.13.0

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A Study of Radiation Effect by Lead Frame Connection for Power Devices

katsuhiko yoshihara, Yoshinari Ikeda, Yuji Iizuka, Mitsuo Yamashita

Session ID: 17A-08
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.15.0

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Fine-pitch Interconnection for Chip-on-Chip Packaging by Applying NCP with Dipped Solder Bump on Electro-less Plating

Watanabe Akihiro, Toshihiro Mori, Akira Yamauchi, Kenzo Hatada

Session ID: 17A-09
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.17.0

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Backside CMP for Three-dimensional Chip Stacking

Yuichi Taguchi, Masataka Hoshino, Kouji Marusaki, Mitsuo Ueno, Yoshihi ...

Session ID: 17A-10
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.19.0

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Buhin naizoukiban

Kazutoku Yamamoto, Kyou Jindai, Yoshiki Hirata, Yasusi Shimada, Yuichi ...

Session ID: 17B-K1
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.21.0

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Buhin naizoukiban

Tsutomu Tsukui

Session ID: 17B-K2
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.23.0

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Whisker Growth Mechanism for Test method

Ichizo Sakamoto

Session ID: 17B-01
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.25.0

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Evaluation of Thermal Fatigue Crack Initiation Lifetime in Solder Joints by Phase Growth Observation

Toshihiko Sayama, Satoko Yamazaki, Takao Mori, Yoshiaki Nagai, Takeshi ...

Session ID: 17B-02
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.27.0

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Thermal Fatigue Evaluation by B-Sn Phase Growth Observation in Sn-3.0Ag-0.5Cu Solder Joints Bonded on Electroless Ni-P/Au Plating

Eiji Kawamoto, Toshihiko Sayama, Takao Mori, Yoshiaki Nagai, Takeshi T ...

Session ID: 17B-03
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.29.0

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The analysis of Influence in the reliability of BGA solder joints

Hirokazu Abe, Qiang Yu, Jae-Chul Jin, Masaki Shiratori

Session ID: 17B-04
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.31.0

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Evaluation method of Lead-free Solder Joints Strength for Wave Soldering after Reflow Soldering

Hiroyuki Takahashi, Kenji Hirohata, Katsumi Hisano, Takashi Kawakami, ...

Session ID: 17B-05
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.33.0

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The Assessment of Drop Impact Reliability for Electronic Device

Toshihiro Tsurusawa, Qiang Yu, Keiji Watanabe, Manabu Kakino, Noriyuki ...

Session ID: 17B-06
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.35.0

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The evaluation of impact reliability for mobile equipments

osamu ido, tadashi tateno, mami nagatake, nobutaka itoh, mitsunori abe ...

Session ID: 17B-07
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.37.0

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Evaluation of Electric Reliability for Resin Embedded Super Connect Level Pattern

makoto sato, Junichiro Yokota, Sachio Yoshihara, Takashi Shirakashi

Session ID: 17B-08
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.39.0

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Deformation evaluation of solder by thermo electro motive force

noboru nakayama, tetsuo kumazawa

Session ID: 17B-09
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.41.0

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Kyukyokunokogatabuhin-no-tourai

Jun Kinoshita

Session ID: 17C-K1
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.43.0

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Denshibuhin Saizensen

Susumu Honda

Session ID: 17C-K2
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.45.0

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Standardization of method for testing mechanical characteristics of lead-free solder

JIS Z 3198-2

Ikuo Shohji, Susumu Hioki

Session ID: 17C-01
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.47.0

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Study on 25 micron pitch and low dimensional change rate flexible circuits

Yoichi Shinba, Futoshi Okuyama, Nobuo Fuji, Yuta Nakano, Kazuya Nishio ...

Session ID: 17C-02
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.49.0

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Flexible circuit boards on which driver ICs for a Liquid Crystal Display (LCD) are mounted have extremely fine lead pattern, and are manufactured with the lead pitch of 35 micron. The number of bumps of ICs is increasing to meet the high resolution of LCDs, which demands much narrower lead pitch. We have developed a flexible circuit board with the pitch of 25 micron using semi-additive process and bonded a high pin-count IC on this board.

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The formation of conductive layer in the deep-recessed trenches using electroless nickel plating

Toshiyuki Okabe, Satoshi Kato, Takanori Tsunoda, Hideo Honma

Session ID: 17C-03
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.51.0

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Connection technology to relax stress with Elastic Conductive Adhesive

Takeshi Sano

Session ID: 17C-04
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.53.0

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Study of lead-free manual soldering method for Automotive

tetsuya hagiwara, takashi serizawa

Session ID: 17C-05
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.55.0

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None flux residue solder bumping by hydrogen ragical reflow

Kenji Maruoka, Tadatomo Suga, Eiji Higurashi, Keisuke Saito, Taizo Hag ...

Session ID: 17C-06
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.57.0

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FEM analysis of deformation and bonding processes of Cu bump

yu kakegawa, Tadatomo Suga

Session ID: 17C-07
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.59.0

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Effects of the temperature, contact load and surface roughness of Cu bump on the strength of low temperature Cu-Cu direct bonding were examined. By means of FEM, we calculated the contact area in the bonding processes between Cu bump and Cu sheet for various temperatures and loads, taking into account the surface roughness of them. The necessary conditions for bonding were discussed and clarified by comparison of the FEM analysis with the results of experiments.

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3-Dimension Measurement Sensor

Norihiko Masuda

Session ID: 17C-08
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.61.0

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Wafer backside processes of through-via fabrication for three-dimensional stacking device

Kouji Marusaki, Yuichi Taguchi, Mitsuo Ueno, Kazumasa Tanida, Mituo Um ...

Session ID: 18A-01
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.63.0

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Development on ultra thin high density SiP

Jun Tsukano, Takehiko Maeda, Keiichirou Kata, Tadanori Shimoto, Kazuhi ...

Session ID: 18A-02
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.65.0

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Reliability of a Wafer Level Packaging Method with Plastic-core Solder Bumps

Rina Murayama, Masato Sumiakwa, Masashi Ogawa, Hiroshi Matsubara

Session ID: 18A-03
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.67.0

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Embedded Wafer Level System in a Package

Osamu Yamagata

Session ID: 18A-04
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.69.0

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Development of support method for thin wafer by glass

Mitsuo Ueno, Tomonori Fujii, Yoshimi Egawa, Yoshihiko Nemoto, Kenji Ta ...

Session ID: 18A-05
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.71.0

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Micro-bump interconnections and materials on 3D stacked LSI for next generation of SiP

YOSHIHIRO TOMITA, Kazumasa Tanida, Mitsuo Umemoto, Kenji Takahashi

Session ID: 18A-06
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.73.0

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Micro-bump interconnect technologies in 20um-pitch have been developed in four and half year from Sep.99 to Mar.03 as a project for the establishment of JISSO technologies to realize the next generation of SiP, that applied to 3D stacked LSI utilizing the electrode plugs through wafers. In this paper, a part of the achievement is introduced accompanied by the results of the researches on the materials such as bumps and underfill resin. This work was performed under the management of ASET supported by NEDO.

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Kinetics of intermetallic growth at lead-free solder / Cu interface

Yasuhiro Kamata, Tadashi Takemoto, Hiroshi Nishikawa, Takamichi Iida

Session ID: 18A-07
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.75.0

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Interfacial reaction between Sn-Cu solder and Cu substrate

jinyu piao, Hiroshi Nishikawa, Tadashi Takemoto

Session ID: 18A-08
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.77.0

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Estimate of Property In Haden and Hygroscopic of CSPmold resin

MAMI NAKADATE, NOBUTAKA ITOH, Osamu Kawauchi

Session ID: 18A-09
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.79.0

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Novel silicone die attach films for stacked package

Manabu Sutoh, Yoshito Ushio, Toyohiko Fujisawa, Yoshinori Taniguchi

Session ID: 18A-10
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.81.0

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Focused on increasing stacked packages such as MCP, 3D-SiP, we developed novel silicone die attach films. The line-up contains "super thin elastomer type" for chip / chip bonding and "gap-filling type" for chip / substrate bonding. This report contains general properties and test results of wafer backside lamination, wire bonding, and reliability test after epoxy molding using these new die attach films.

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Entry Sheet for Mechanical Drilling

Film sheet which is suitable for ultra-small drilling

KATSUHIKO KATSUMA, TSUKASA IZUMI

Session ID: 18A-11
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.83.0

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Photosensitivity of Thick Photosensitive Multiblock Copolymerized Polyimide

Katsuya Kikuchi, Shigemasa Segawa, Eun-Sil Jung, Hiroshi Nakagawa, Kaz ...

Session ID: 18A-12
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.85.0

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Development of enviroment friendly FR-1 material for lead-free solder by useing a reflow machine

masao uesaka, Shigeyuki Yagi, Hiroyuki Matsuoka

Session ID: 18A-13
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.87.0

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Development of Highly Heat Resistant Halogen-Free Substrate Material

Kousuke Hirota, Kenji Shima, Takashi Iiyama

Session ID: 18A-14
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.89.0

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Dielectric properties of aramid-epoxy resins

Part 1: Observation of internal electric field profiles

Kaori Fukunaga, Kenji Okamoto, Takashi Maeno

Session ID: 18A-15
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.91.0

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Internal space charge, and electric field profiles of aramid-epoxy resin were observed by using the pulsed electroacoustic (PEA) method. Under dc voltage applications, ionic charges inside the specimen moved towards both electrodes at room temperature and humidity. The profiles depend on the types of aramid randum chopped fibres.

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Low loss and low Z-CTE materials for Multi-layer PCBs

kiyotaka komori, tatsuya watanabe, shoji hashimoto, hiroharu inoue, hi ...

Session ID: 18A-16
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.93.0

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The Development of High Density Substrate Material for Semiconductor Packaging

Tadasuke Endo, Takeshi Hosomi, Takayuki Baba

Session ID: 18A-17
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.95.0

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Development of Dry Film Resist for Direct Imaging Exposure

Yousuke Hata, Tomoko Yoshida, Shinji Arihisa, Toru Mori, Shouichirou T ...

Session ID: 18A-18
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.97.0

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Technology Roadmap for Optical packaging

Kazuhiko Kurata, Ichirou Hatakeyama, Kazunori Miyoshi, Takanori Shimiz ...

Session ID: 18B-01
Published: 2004
Released on J-STAGE: September 01, 2004

DOIhttps://doi.org/10.11486/ejisso.18.0.99.0

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