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The 17th JIEP Annual Meeting

Displaying 101-144 of 144 articles from this issue

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Effect of a Catalyzing Process for the Improvement of Solderability

Tomoyuki Yamamoto, Hideto Watanabe, Hideo Honma

Session ID: 14A-03
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.101.0

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Study of Whisker Free Sn Plating

Takashi Tohyama, Kanae Tokio, Yuichiro Umeda, Yoshiaki Muramatsu

Session ID: 14A-04
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.102.0

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Bright Acid Copper Technology for Via Filling

Hiroshi Ishizuka, Hideki Hagiwara, Megumi Maruyama, Nobuo Sakagawa, Ry ...

Session ID: 14A-05
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.103.0

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Heat-resistant Protective Tapes for Back-grinding Thin Wafers

Kouichi Nagamoto, Tatsuya Izumi, Hironobu Fujimoto, Kazuhiro Takahashi ...

Session ID: 14A-06
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.104.0

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Anisotropic conductive sheet fabricated with a porous fluororesin material

yasuhito masuda

Session ID: 14A-07
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.105.0

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Vacuum bonding properties of Si/Glass and Si/Si for three dimensional stacking LSI processes

Mitsuo Ueno, Kouji Marusaki, Yuichi Taguchi, Yoshihiko Nemoto, Masatak ...

Session ID: 14A-08
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.106.0

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Effect of various factors for wire-bondability on ultra-thin embedded package

Jun Tsukano, Takehiko Maeda

Session ID: 14A-10
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.107.0

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Feasibilities on diffusion between copper and tin utilizing variable frequency microwave (VFM) cure on micro-bump interconnections

YOSHIHIRO TOMITA, MITSUO UMEMOTO, YOSHIHIKO NEMOTO, MASAMOTO TAGO, KEN ...

Session ID: 14A-11
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.108.0

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Micro Cu bump with tin-cap is one of the candidate interconnections for 3D stacked LSI. First, it was found the diffusion between copper and tin at the curing in variable frequency microwave (VFM) oven was faster than at the heating on a hot-plate. Moreover, IMC between tin and copper after the low-temperature bonding as Cu6Sn5 transit to approximately uniform Cu3Sn by curing in VFM oven. Then, the possibilities on the micro-joint with the VFM cure were found out. This work was performed under the management of ASET supported by NEDO.

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Fabrication Technique of Fine Wiring Structure by Electrodeposited Polyimide

KAZUHIKO TOKORO, HIROSHI NAKAGAWA, KATSUYA KIKUCHI , Eunl-Sil Jung, SH ...

Session ID: 14A-12
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.109.0

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Fabrication of Fine High-Density Strip-Line Structure Using Photosensitive Polyimide Insulation layer for LSI packages

Katsuya Kikuchi, Shigemasa Segawa, Eun-Sil Jung, Hiroshi Nakagawa, Kaz ...

Session ID: 14A-13
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.110.0

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Interconnection of FPC using non-conductive adhesive films

Resin Encapsulated Flex Interconnection(REX)

Kohichiro Kawate

Session ID: 14A-14
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.111.0

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Resin encapsulated flex interconnection (REX) will be reviewed. At first, flex circuits are pressed by a mold to form structured surface on the circuits. Then the flex circuits can be bonded on PCB (printed circuit board) through a non-conductive thermosetting adhesive film. By heat press, the structures on the flex circuits contact with circuits on PCB through the adhesive and plastic deformation occur. The contact point is also metallurgical bonded at heat press.

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development of stack packages with the encapsulation film

kazuki uwada, yuuji hotta, akiko matsumura

Session ID: 14A-15
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.112.0

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Study on stacked-chips assembly with Flip-chip connection

AKIKO MATSUMURA, KAZUKI UWADA, YUJI HOTTA

Session ID: 14A-16
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.113.0

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DEVELOPMENT OF PBGA WITH HIGH SPEED I/O

HIDEHARU SAKODA, AKIRA OKADA, FUMIHIKO TANIGUCHI

Session ID: 14A-17
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.114.0

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Wirebond-type PBGA which is used forpackaging high speed I/O signal linewith 622MHz was developed. conventionally,expensive packagehas been adopted for ASIC devices withhigh speed I/O signal line.Now we succeeded in reducing packagingcost by reducing length of high speedsignal transmission line thoroughly andinserting adequate power/ground planeinto interposer.In the volume production,preventionof wire flow at molding process was one of the main subjects to be overcome.

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Development of Stacked Packaging Using Comperssion Type Flip Chip Technology

Kazuto Nishida, Kazumichi Shimizu, Takashi Yui, Hajime Honma, Izumi Ok ...

Session ID: 14A-18
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.115.0

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A stacked device called SEP was developed to drastically increase LSI density relative to its area on the circuit board.
The bottom-side chip was made into a flip-chip structure and attached to the substrate by the NSD method, which involves the use of stud-bumps and adhesive encapsulation film. On the top of this flip-chip LSI, another LSI was stacked and interconnected by using low-profile wire-bonding technology.
This packaging technology was able to provide a super multi-pin system LSI with more than 600 pins.
By adopting this package in a mobile communication product, the required package area on the circuit board could be reduced by 35%.

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Thermal resistance analysis of Package Stacked CSP for Three-dimensional SIP (System-in-Package)

Tomoyo Maruyama

Session ID: 14A-19
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.116.0

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DEVELOPMENT OF 3-DIMENSIONAL TYPE MULTI CHIP PACKAGE

FUMIHIKO ANDO, MITSUHISA WATANABE, KAZUYUKI AIBA, YOSHIKAZU KUMAGAYA, ...

Session ID: 14A-20
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.117.0

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Now Stacked-MCP which carries a fewchips are mass produced. However, in this former tipe package, it is clear that there is a limit to a number of chips,line/space on board for further performance and capacity. For this problem, Fujistu proposes PS-MCP. This is three dimensional package which carries some Stacked-MCP packages.This paper introduces the structure, measures for some ploblems through development and our plan of PS-MCP.

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An LSI Package with Optical I/O Interfaces

Ichiro Hatakeyama, Takashi Yoshikawa, Kazunori Miyoshi, Kazuhiko Kurat ...

Session ID: 14B-02
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.119.0

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10Gbit/s/channel parallel optical transmitter and receiver modules

Masato shishikura

Session ID: 14B-03
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.120.0

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Actlive Interposer technologies in Optoelectronic packaging

masahiro okabe, takashi mikawa, kenji hiruma, masao kinoshita, takeshi ...

Session ID: 14B-04
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.121.0

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Low cost board level optical interconnection using polyimide waveguide film

Tsuyoshi Shioda, Nobuhiro Takamatsu, Kenji Suzuki

Session ID: 14B-05
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.122.0

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A low cost intra-board level optical interconnection was developed using a fluorinated polyimide waveguide film and conventional printed wiring board (PWB). We proposed that the edges of the multi-mode waveguide film with the core size of about 90um width and 20um height coupled directly to a commercialized 850nm multi-mode vertical-cavity-surface-emitting-laser (VCSEL) and photodiode (PD) by the developed passive alignment technique using an appropriate adhesive. Then the VCSEL and PD connected by the waveguide film were mounted on a PWB, bending the waveguide film. This technique was very simple and low cost technique. The total loss of two coupling was obtained to be about 3dB. The data rate higher than 1Gbps was transmitted using the PWB with the optical interconnection.

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Self-Written Technology of Optical Connection between Optical Devices and Wirings

Noritoshi Watanabe, Kentarou Miyazato, Yoshikazu Murata, Haruki Ogasaw ...

Session ID: 14B-06
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.123.0

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Proposal of Optical Pin for Parallel Optical Interconnection

Noritoshi Watanabe, Kentarou Miyazato, Yoshikazu Murata, Yusuke Oyama, ...

Session ID: 14B-07
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.124.0

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Application of Micro Lens Array to Optical Surface Mount Technology

yusuke oyama, kentaro miyazato, yosikazu murata, noritosi watanabe, os ...

Session ID: 14B-08
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.125.0

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Development of Optoelectronic Hybrid Boards using Optical Fibers

Ken-ichi Higashiura, Makoto Kato

Session ID: 14B-09
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.126.0

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In recent years, as the transmission speed increases, optical interconnections is desired not only in the device but also in the board-level. Therefore, an optical wiring layers are accumulated to the electric wiring board, and the optoelectronic hybrid boards which replaces a part of the electric wiring with optical wiring is paid to attention. For the achievement example, we have previously proposed a new structure and a method of the optoelectronic hybrid boards that endures the solder reflow process by optical components is embedded in a glass-epoxy circuit board.

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Guided-mode-selective focusing grating coupler for ultra-broad-band chip-to-chip optical interconnects

Yoshitaka Imaoka, Junpei Ohmori, Mei Hamada, Shogo Ura, Kenji Kintaka

Session ID: 14B-10
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.127.0

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VCSEL array driver circuit for optical components

HIDETOSHI NUMATA, YOSHITAMI SAKAGUCHI, YOICHI TAIRA

Session ID: 14B-11
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.128.0

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Evaluation of Reliability for Optical connector

yuichi aoki, kishichi sasaki, kiyoyuki mutaguchi

Session ID: 14B-12
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.129.0

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Electroless Nickel plating for optical fiber with nm probe

Yuichi Saito, Shuji Mononobe, Shingo Watanabe, Shuhei Miura, Hideo Hon ...

Session ID: 14B-13
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.130.0

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High Speed Bump Inspection Method Using X-ray Fluoroscopy

Atsushi Teramoto, Takayuki Murakoshi, Isao Horiba

Session ID: 14C-02
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.131.0

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AOI technology of the chip mounted board

KIYOSHI HAYAKAWA, MASAMICHI WADA

Session ID: 14C-03
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.132.0

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Wettability Evaluation Method by Fillet Image Analysis

tsuyoshi inage

Session ID: 14C-04
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.133.0

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Visualization of Solder Joint Shape in a Wafer Level CSP Using Dry-Contact Ultrasound

Hironori Tohmyoh, Masumi Saka

Session ID: 14C-05
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.134.0

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Probe marks by the Flying probe tester

Tadashi Tomoi

Session ID: 14C-06
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.135.0

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A simple calibration method for measuring electric current waveforms using a microstrip line

Toshiki Shimasaki, Katsuji Kobayashi, Norio Masuda, Naoya Tamaki, Yosh ...

Session ID: 14C-07
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.136.0

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The non-contact measurement method standardized by the IEC to measure of high-frequency current spectra on a trace connected to LSI power supply leads is used to evaluate electromagnetic interference (EMI). However, spectrum measurement is useful only for estimating the time-averaged behavior of LSIs. This paper describes a simple calibration method for measuring the electric current waveform flowing in the strip conductor of a microstrip line. This method is useful for evaluating the time - varying behavior of LSIs. The measurement errors for this method are also evaluated.

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Fabrication and packaging of MEMS mirror array

Renshi Sawada, Eiji Higurashi, Johji Yamaguchi, Akira Shimizu, Tsuyosh ...

Session ID: 14C-09
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.137.0

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A Research of Actuators for Micromirror Control

Qiang Yu, Koji Ishikawa, Hiroki Mamiya, Masaki Shiratori

Session ID: 14C-10
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.138.0

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Development of Electric Circulate Devices equipped with Micro Fluid Chip

TAKAAKI ISODA, NAOKI TAKAHARA, RYUHEI MORI, FUYUMI ITO, MIKA YAMADA, M ...

Session ID: 14C-11
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.139.0

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A world-to-chip socket with built-in valves for testing microfluidic device

Zhen YANG, Ryutaro MAEDA

Session ID: 14C-12
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.140.0

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Application of intra-body communication for wearable devices

KEN SASAKI, KEISUKE HACHISUKA, HIROSHI HOSAKA, KIYOSHI ITAO

Session ID: 14C-13
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.141.0

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Room Temperature Direct Bonding of Optical Microdevices Using Surface Activated Bonding Method

Ryoko Ochiai, Makoto Tomita, Toshihiro Itoh, Tadatomo Suga, Eiji Higur ...

Session ID: 14C-14
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.142.0

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Fabrication and Evaluation of Feed-throughs in Silicon substrate

Hideyuki Wada, Tatsuo Suemasu, Satoshi Yamamoto, Kazuhisa Itoi, Takesh ...

Session ID: 14C-15
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.143.0

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Surface Activated Bonding of Sputter Deposited Platinum Films on Wafers

Hideki Takagi, Ryutaro Maeda

Session ID: 14C-16
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.144.0

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Low Contact Force Probing on Cu Electrodes

Toshihiro Itoh, Kenichi Kataoka, Katsuya Okumura, Tadatomo Suga

Session ID: 14C-17
Published: 2003
Released on J-STAGE: October 14, 2003

DOIhttps://doi.org/10.11486/ejisso.2003.0.145.0

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