[in Japanese]

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[in Japanese]

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[in Japanese]

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[in Japanese]

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[in Japanese]

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A low-speed detection method using a fail-safe counter is proposed. Specific features of this proposed method are, firstly, the adoption of digital counter circuits tor detection or low-speed, and, secondly, the diagnosis of the digital counter circuit and its result output as dynamic signals to a band-pass filter and a charge pump circuit. Only when the motor speed gets lower than the predetermined speed and no parts of the digital counter circuit malfunction, dynamic signals with the band-pass frequency are provided to the filter and a DC signal is eventually output as the low-speed detection results in a fail-safe manner. Safety analyses of this fail-safe counter have been carried out, and a fail-safe window comparator which checks the DC signal level from the fail-safe counter has been added to the charge pump circuit as a countermeasure against two specific critical failure modes. The safe speed monitoring (SSM) and safely limited speed (SLS) functions are important designated safety functions which the IEC 61800-5-2 requires of electrical power drive systems, and these functions are realized by the fail-safe counter in an inherently safe manner.

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