[in Japanese]

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[in Japanese]

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[in Japanese]

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[in Japanese]

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[in Japanese]

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[in Japanese]

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[in Japanese]

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A fail-safe relay drive circuit, which outputs only under no-malfunction situations and which outputs to two relays with some time difference to avoid the common mode failure of the welding of contacts, is proposed. The output and the correct safe timing of driving/de-driving the relays is achieved by CMOS inverters and linear regulators, as well as the relay drive circuit with constant output voltage by a transformer. In introducing CMOS inverters, which are the most common logic, to safety-related applications, countermeasures against self-oscillation in the case of input open-faults are the main concern, and this can be addressed by providing the electrical source and the input signal for the inverter pins with the same timing, or adding a capacitor and metal shield to the CMOS inverter input. The relay drivers output high powered with stability and band-pass filter characteristics, and booting ground voltage level of ICs by the similar transformers increases tolerance to line-cross at lines to relays or noise by EMC coupling within the circuit. This paper describes the relay drive circuit for the safe operation order and the fail-safe measures to realise the function, as well as safety analyses of these, and reveals the validity and expandability of these safety measures.

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