A one-dimensional lattice of tunnel-diode oscillators is investigated for potential high-speed frequency divider. In the evolution of the investigated lattice, the high-frequency oscillation dominates over the low-frequency oscillation. When a base oscillator is connected at the end, and generates oscillatory signals with a frequency higher than that of the synchronous lattice oscillation, the oscillator output begins to move in the lattice. This one-way property guarantees that the oscillation dynamics of the lattice have only slight influence on the oscillator motion. Moreover, counter-moving pulses in the lattice exhibit pair annihilation through head-on collisions. These lattice properties enable an efficient frequency division method. Herein, the operating principles of the frequency divider are described, along with a numerical validation.

The performance of a network router/switch has improved significantly over past decades with explosively increasing internet and data center traffic. The performance of a router heavily depends on the memory system, e.g. DRAM based packet buffers, which often limits the scalability of a router. However, a widening gap between memory I/O bus and memory cell array speed and decreasing row buffer locality from increasing channels and banks severely reduce the performance gain from state-of-the-art memory technology such as DDR4 or HBM2 DRAM. Prior works improved memory bandwidth by maintaining SRAM-based per-queue or per-bank input/output buffers in the memory controller to support a DRAM-based packet buffer. The buffers temporarily store packets when bank conflicts occur but are unable to prevent interference-inducing traffic from thrashing DRAM's row buffers. In this study, we directly integrate SRAM into the DRAM-based packet buffer and map those packets degrading row buffer locality of DRAM into SRAM. This maximizes locality and parallelism of DRAM accesses. The proposed scheme can benefit any existing schemes. Experimental results show 22.41% improvement over the best existing scheme for a single channel in terms of the memory bandwidth utilization under harsh congested scenarios.

This paper reports a high-quality hardware-friendly integer motion estimation (IME) scheme. According to different characteristics of CTU content, the proposed method adopts different adaptive multi-resolution strategies coupled with accurate full-PU modes IME at the finest level. Besides, by using motion vector derivation, IME for the second reference frame is simplified and hardware resource is saved greatly through processing element (PE) sharing. It is shown that the proposed architecture can support the real-time processing of 4K-UHD @60fps, while the BD-rate is just increased by 0.53%.