We report a fast single element nonvolatile memory that employs amorphous to crystalline phase change. Temperature change is induced within a single electronic element in confined geometry transistors to cause the phase change. This novel phase change memory (PCM) operates without the need for charge transport through insulator films for charge storage in a floating gate. GeSbTe (GST) was employed to the phase change material undergoing transition below 200°C. The phase change, causing conductivity and permittivity change of the film, results in the threshold voltage shift observed in transistors and capacitors.

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We propose a new cone-type DRAM cell as a 1T DRAM cell. The superiority of cone shape is already reported, in that the electric field concentration effect encourages impact ionization phenomenon. So the device has improved DRAM characteristics compared with cylinder type 1T DRAM Cell (SGVC Cell). To confirm the memory operation of the cone-type DRAM cell, simulation works were carried out. Also, retention characteristic shows the device can be used practically.

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Recently, the 3-dimensional (3-D) vertical Floating Gate (FG) type NAND flash memory cell arrays with the Extended Sidewall Control Gate (ESCG) was proposed [7]. Using this novel structure, we successfully implemented superior program speed, read current, and less interference characteristics, by the high Control Gate (CG) coupling ratio with less interference capacitance and highly electrical inverted S/D technique. However, the process stability of the ESCG structure has not been sufficiently confirmed such as the variations of the physical dimensions. In this paper, we intensively investigated the electrical dependency according to the physical dimensions of ESCG, such as the line and spacing of ESCG and the thickness of barrier oxide. Using the 2-dimentional (2-D) TCAD simulations, we compared the basic characteristics of the FG type flash cell operation, in the aspect of program speed, read current, and interference effect. Finally, we check the process window and suggest the optimum target of the ESCG structure for reliable flash cell operation. From above all, we confirmed that this 3-dimensional vertical FG NAND flash memory cell arrays using the ESCG structure is the most attractive candidate for terabit 3-D vertical NAND flash cell array.

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Due to the aggressive scaling of non-volatile memories, “charge-trap memories” such as MONOS-type memories become one of the most important targets. One of the merits of such MONOS-type memories is that they can trap charges inside atomic-scale defect sites in SiN layers. At the same time, however, charge traps with atomistic scale tend to induce additional large structural changes. Hydrogen has attracted a great attention as an important heteroatom in MONOS-type memories. We theoretically investigate the basic characteristics of hydrogen-defects in SiN layer in MONOS-type memories on the basis of the first-principles calculations. We find that SiN structures with a hydrogen impurity tend to reveal reversible structural change during program/erase operation.

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Resistive switching of metal-insulator-metal (MIM), consisting of a metal-organic chemical vapour deposition (MOCVD) TiO₂ layer sandwiched between Pt electrodes, has been measured systematically before and after thermal annealing in different ambiences. With H₂ annealing at 400°C, the current level in the high-resistive state (HRS) significantly decreased while little change in the low-resistive state (LRS) was observed. As a result, the switching ratio over 7 orders of magnitude at the current level was obtained. From the analysis of current-voltage (I-V) characteristics in HRS and LRS, we found that the LRS was characterized with an ohmic conduction, while in the HRS after H₂ annealing, charge trapping became significant as a result of a significant decrease in the current level. In a separate experiment, a partial reduction in TiO₂ was detected using high-resolution X-ray photoelectron spectroscopy (XPS) after resistant-state switching from HRS to LRS by using a Hg probe as a top electrode, which is associated with filament formation.

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Several kinds of capacitor-less DRAM cells based on planar SOI-MOSFET technology have been proposed and researched to overcome the integration limit of the conventional DRAM. In this paper, we propose the Floating Body type DRAM cell array architecture with the Vertical MOSFET and discuss its basic operation using a 3-D device simulator. In contrast to previous planar SOI-MOSFET technology, the Floating Body type DRAM with the Vertical MOSFET achieves a cell area of 4F² and obtain its floating body cell by isolating the body from the substrate vertically by the bottom-electrode. Therefore, the necessity for a SOI substrate is eliminated. In this paper, the cell array architecture of Floating Body type 1T-DRAM is proposed, and furthermore, the basic memory operations of read, write, and erase for Vertical type 1 transistor (1T) DRAM in the 45nm technology node are shown. In addition, the retention and disturb characteristics of the Vertical type 1T-DRAM are discussed.

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We have demonstrated high mobility MOS transistors on high quality epitaxial SiGe films selectively grown on Si (100) substrates. The hole mobility enhancement afforded intrinsically by the SiGe channel (60%) is further increased by an optimized Si cap (40%) process, resulting in a combined ∼100% enhancement over Si channels. Surface orientation, channel direction, and uniaxial strain technologies for SiGe channels CMOS further enhance transistor performances. On a (110) surface, the hole mobility of SiGe pMOS is greater on a (110) surface than on a (100) surface. Both electron and hole mobility on SiGe (110) surfaces are further enhanced in a <110> channel direction with appropriate uniaxial channel strain. We finally address low drive current issue of Ge-based nMOSFET. The poor electron transport property is primarily attributed to the intrinsically low density of state and high conductivity effective masses. Results are supported by interface trap density (D_it) and specific contact resistivity (ρ_c).

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A stacked structure consisting of ∼1nm-thick MgO and 4nm-thick HfO₂ was formed on thermally grown SiO₂/Si(100) by MOCVD using dipivaloymethanato (DPM) precursors, and the influences of N₂ anneal on interfacial reaction and defect state density in this stacked structure were examined. The chemical bonding features of Mg atom were evaluated by using an Auger parameter independently of positive charge-up during XPS measurements. With Mg incorporation into HfO₂, a slight decrease in the oxidation number of Mg was detectable. The result suggests that Mg atoms are incorporated preferentially near oxygen vacancies in the HfO₂, which can be responsible for a reduction of the flat band voltage shifts observed from C-V characteristics.

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In this paper, we compare 1/f noise characteristics of High-k/Metal Gate MOSFET and SiON/Poly-Si Gate MOSFET experimentally, and evaluate the time fluctuation of drive current. These MOSFETs are fabricated with 65nm CMOS process, and their gate lengths (Lg) are 130nm. Specifically, we focus on the dependency of the time fluctuation of drive current on channel width (W) and temperature (T). First, we evaluate the dependency on channel width. In the case of SiON/Poly-Si Gate MOSFET, when the channel width is narrow such as W=200nm and W=250nm, Power Spectrum Density (PSD) depends on 1/f² at two frequency regions. Moreover, as the channel width is wide such as W=300nm, W=500nm and W=1000nm, PSD depends on 1/f and the value of PSD shifts lower. This is a new phenomena observed for the first time. On the other hand, in the case of High-k/Metal Gate MOSFET, the value of PSD is about 100 times larger than that of SiON/Poly-Si Gate MOSFET. Moreover, there is no dependency of PSD on channel width ranges from 150nm to 1000nm. Second, we evaluate the dependency on temperature. In the case of SiON/Poly-Si Gate MOSFET, when the temperature (T) is lowered from T=27°C to T=-35°C, the dependency changes from the 1/f dependency to the 1/f² dependency at two different frequency regions. This is also a new phenomena observed for the first time. However, in the case of High-k/Metal Gate MOSFET, there is no dependency of PSD on temperature ranges from 27°C to -35°C. These results are useful knowledge for designing future LSI, because PSD dependency shows different characteristics when both channel width and temperature are changed.

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We propose the collective electron tunneling model in the electron injection process between the Nano Dots (NDs) and the two-dimensional electron gas (2DEG). We report the collective motion of electrons between the 2DEG and the NDs based on the measurement of the Si-ND floating gate structure in the previous studies. However, the origin of this collective motion has not been revealed yet. We evaluate the proposed tunneling model by the model calculation. We reveal that our proposed model reproduces the collective motion of electrons. The insight obtained by our model shows new viewpoints for designing future nano-electronic devices.

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We have studied the transport property of the Vertical MOSFET (V-MOSFET) with an impurity from the viewpoint of quantum electron dynamics. In order to obtain the position dependence of impurity for the electron transmission property through the channel of the V-MOSFET, we solve the time-dependent Shrödinger equation in real space mesh technique We reveal that the impurity in the source edge can assist the electron transmission from the source to drain working as a wave splitter. In addition, we also reveal the effect of an impurity in the surface of pillar is limited because of its dimensionality. Furthermore, we obtained that the electron injection from the source to the channel becomes difficult due to the energy difference between the subbands of the source and the channel. These results enable us to obtain the guiding principle to design the V-MOSFET in the 10nm pillar. The results enable us to obtain the guiding principle to design the V-MOSFET beyond 20nm design rule.

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In order to realize Integrated Circuits (IC) with operation over the 10GHz range, conventional CMOS logic faces critical issues, such as increasing power consumption, and difficulty to aggressively scale the device size and so on. To overcome this issue, we have proposed Current Controlled-MOS Current Mode Logic (CC-MCML) to realize the reduction of power consumption and the enhancement of the operation speed in logic circuits without scaling the gate length of the MOSFET, and confirmed the performance of these circuits both theoretically and experimentally. In the CC-MCML it is extremely important to control the input voltage of the MOSFET used as the constant current source in order to make the base voltage of the input signal and the output signal equivalent. In this paper, we propose CC-MCML/MTJ (Magnetic Tunnel Junction) circuit, which is one type of nonvolatile memory hybrid circuit technology. A more stable and precise operation is realized by cutting the range of the input voltage of the constant current source, and it is shown that the operation of CC-MCML/MTJ Hybrid Circuit enables us to suppress the base voltage difference due to the Vth fluctuation in comparison with the conventional CC-MCML. These results imply the high potential of Si-CMOS/Spintronics Hybrid technologies for future IC.

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As the integration density and capacitance of semiconductor devices have increased, high-dielectric (High-k) materials have attracted considerable attention. We investigated the dependence of threshold voltage (V_th) characteristics of the High-k/Metal Gate MOSFET fabricated with 65nm CMOS process on the temperature, in comparison to conventional SiON/Poly-Si Gate MOSFET. Two aspects including the Fermi level and the channel mobility in MOSFET are discussed in details. Furthermore, the influence of threshold voltage characteristics of the High-k/Metal Gate MOSFET on the logic threshold voltage (V_th-inv) of CMOS inverter is reported in this paper.

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We have succeeded in fabricating 180nm Current Controlled MOS Current Mode Logic (CC-MCML) and verified the stable circuit operation of 180nm CC-MCML under threshold voltage fluctuations by measurement. The performance stability of the CC-MCML inverter under the fluctuations of threshold voltage of NMOS and PMOS is evaluated from the viewpoint of diminishing the bias offset voltage ΔV_B. The ΔV_B, that is defined as (base voltage of output waveform) - (base voltage of input waveform), is a key design parameter for differential circuit. It is shown that when the threshold voltage of NMOS fluctuates in the range of 0.53V to 0.69V, and threshold voltage of PMOS fluctuates in the range of -0.47V to -0.67V, the CC-MCML technique is able to suppress ΔV_B within only 30mV, where as the conventional MCML technique caused maximum ΔV_B of 1.0V. In this paper, it is verified for the first time that the fabricated CC-MCML is more tolerant against the fluctuations of threshold voltages than the conventional MCML.

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In order to realize stable n-type characteristics of pentacene for applying to the organic complementary metal-oxide-semiconductor field-effect transistors (CMOS), we have fabricated pentacene based MOS diodes using ultra-thin Yb layer such as 0.5-3nm between gate insulator and pentacene. From the results of capacitance-voltage (C-V) measurements, excellent n-type C-V characteristics of the devices with 1 and 2nm-thick Yb were observed even though the devices were measured in air. These results suggested that the n-type semiconductor characteristics of pentacene are able to be improved by the thin Yb interfacial layer. Furthermore, the improved n-type characteristics of pentacene will enable the fabrication of flexible complementary logic circuits utilizing one kind organic semiconductor.

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We studied the interaction of Bis-diethylaminosilane (SiH₂[N(C₂H₅)₂]₂, BDEAS) with a hydroxylized Si (001) surface for SiO₂ thin-film growth using density functional theory (DFT). BDEAS was adsorbed on the Si surface and reacted with the H atom of hydroxyl (-OH) to produce thedi-ethylaminosilane (-SiH₂[N(C₂H₅)₂], DEAS) group and di-ethylamine (NH(C₂H₅)₂, DEA). Then, DEAS was able to react with another H atom of -OH to produce DEA and to form the O-(SiH₂)-O bond at the inter-dimer, inter-row, or intra-dimer site. Among the three different sites, the intra-dimer site was the most probable when it came to forming the O-(SiH₂)-O bond.

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In order to reduce PtSi Schottky barrier height (SBH) for electron, we investigated modulation of PtSi work function by alloying with low work function metal, such as Hf (3.9eV) and Yb (2.7eV). Pt (10-20nm)/Hf, Yb (0-10nm)/n-Si(100) stacked structures were in-situ deposited at room temperature by RF magnetron sputtering method. In case of Pt_xHf_1-xSi formed at 400°C/60min annealing in N₂, SBH for electron was reduced from 0.85eV to 0.53eV with Hf thickness without increase of sheet resistance. Yb incorporation also affected the SBH modulation, however, the sheet resistance increased with increase of Yb thickness.

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For analog applications, the Metal-Insulator-Metal (MIM) capacitance has to be measured at a much higher resolution than using the conventional methods, i.e. to a sub-femto level. A new robust mismatch measurement technique is proposed, which is more accurate and robust compared to the conventional Floating Gate Capacitance Measurement (FGCM) methods. A capacitance mismatching measurement methodology based on Vs is more stable than that based on Vf because the influence of pre-existing charge in the floating-gate can be cancelled in the slope of ΔVs/ΔVf based on Vs. The accuracy of this method is evaluated through silicon measurement in a 0.13µm technology. It shows that, compared to the ideal value, the average of the new method are within 0.12% compared to 49.23% in conventional method while the standard deviation is within 0.15%.

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We report on the fabrication of coplanar dual-gate ZnO thin-film transistors with 200-nm thickness SiN_x for both top and bottom dielectrics. The ZnO film was deposited by RF magnetron sputtering on SiO₂/Si substrates at 100°C. And the thickness of ZnO film is compared with 100-nm and 40-nm. This TFT has a channel width of 100-µm and channel length of 5-µm. The fabricated coplanar dual-gate ZnO TFTs of 40-nm-thickness exhibits a field effect mobility of about 0.29cm²/V s, a subthreshold swing 420mV/decade, an on-off ratio 2.7×10⁷, and a threshold voltage 0.9V, which are greatly improved characteristics, compared with conventional bottom-gate ZnO TFTs.

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This work focuses on a study of strain effects in resistor stress sensors fabricated on (001) silicon and their influences on the determination of piezoresistive (pi) coefficients for the precise measurements of die stresses in electronic packages. We obtained the corrected values of the pi-coefficients by considering the strain effects, without which more than 50% discrepancies may be induced.

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A novel NMOS Electrostatic Discharge (ESD) clamp circuit is proposed for a 0.35µm Bipolar-CMOS-DMOS (BCD) process. The proposed ESD clamp has a non-snapback characteristic because of gate-coupled effect. This proposed ESD clamp circuit is developed without additional components made possible by replacing a capacitor with an isolated parasitic capacitor. The result of the proposed ESD clamp circuit is measured by 100ns Transmission Line Pulse (TLP) system. From the measurement, it was observed that the proposed ESD clamp has approximately 40% lower triggering voltage compared to the conventional gate-grounded NMOS ESD clamp. This is achieved without degradation of the other ESD design key parameter. The proposed ESD clamp also has high robustness characteristics compared to the conventional RC-triggered NMOS ESD clamp circuit.

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A switched-capacitor integrator based on dynamic source follower amplifiers has been proposed. Integrator operation has been confirmed and analyzed by assuming 0.18-µm CMOS technology. The integrator can reduce the number of elements considerably compared with conventional ones using operational amplifiers. As a result, the power dissipation of proposed integrator can be reduced to approximately one-eighth that of conventional integrators. The integrator is applied to a second-order ΔΣ modulator, and its successful operation has been confirmed by transistor-level circuit simulation.

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In this work, a V-band low noise amplifier (LNA) is developed in a commercial 0.13µm RFCMOS technology. Common-source (CS) topology, known to show a better noise performance than the cascode topology, was adopted and 4-stage was employed to achieve a sufficient gain at the target frequency near the cutoff frequency f_T. The measured gain was 18.6dB with V_DD=1.2V and increased up to 20.2dB with V_DD=1.8V at 66GHz. The measured NF showed a minimum value of 7.0dB at 62GHz. DC power consumption was 24mW with V_DD=1.2V. The size of the fabricated circuit is as compact as 0.45mm × 0.69mm. This work was further extended to investigate the effect of dummy fills on LNA performance. An identical LNA, except for the dummy fills formed very close to (and under) the metal lines of spiral inductors and interconnects, was also fabricated and compared with the standard LNA. A peak gain degradation of 3.6dB and average NF degradation of 1.3dB were observed, which can be ascribed to the increased mismatch and line loss due to the dummy fills.

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High-power protection switch utilizing a new stub/line selectable configuration is presented. By employing the proposed circuit topology, the insertion loss at receiving mode and the power handling capability at transmitting mode can be independently designed. Therefore, the proposed circuit is able to achieve low insertion loss at receiving mode while keeping high-power performance at transmitting mode. To verify this methodology, MMIC switch has been fabricated in Ka-band. The circuit has achieved the insertion loss of 2dB, the isolation of 25dB, and the power handling capability of 40dBm at 5% bandwidth.

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Tunnel diodes are some of 2-port devices with negative differential resistance (NDR). In this paper, we propose a low insertion loss isolator, which can be designed to operate up to sub-millimeter region, by using resonant tunneling diodes (RTDs) and a HEMT. Small-signal analyses are performed to confirm insertion loss and unidirectional characteristics for the proposed active isolator. It is found that unidirectional amplifications as well as isolation characteristics could be expected below sub-millimeter waveband as a result of numerical calculations.

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We have investigated the effect of deoxyribonucleic acid (DNA) adsorption on a graphene field-effect-transistor (FET) device. We have used graphene which is grown on a Ni substrate by chemical vapour deposition. The Raman spectra of our graphene indicate its high quality, and also show that it consists of only a few layers. The current-voltage characteristics of our bare graphene strip FET show a hole conduction behavior, and the gate sensitivity of 0.0034µA/V, which is reasonable with the size of the strip (5×10µm²). After the adsorption of 30 base pairs single-stranded poly (dT) DNA molecules, the conductance and gate operation of the graphene FET exhibit almost 11% and 18% decrease from those of the bare graphene FET device. The observed change may suggest a large sensitivity for a small enough (nm size) graphene strip with larger semiconducting property.

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In this paper, we report the fabrication and device characteristics of InP/InGaAs double heterojunction bipolar transistors (DHBTs) with buried SiO₂ wires. The SiO₂ wires were buried in the collector and subcollector layers by metalorganic chemical vapor deposition toward reduction of the base-collector capacitance under the base electrode. A current gain of 22 was obtained at an emitter current density of 1.25MA/cm² for a DHBT with an emitter width of 400nm. The DC characteristics of DHBTs with buried SiO₂ wires were the same as those of DHBTs without buried SiO₂ wires on the same substrate. A current gain cutoff frequency (f_T) of 213GHz and a maximum oscillation frequency (f_max) of 100GHz were obtained at an emitter current density of 725kA/cm².

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This paper reports the DC and RF characteristics of AlN/GaN MOS-HEMTs passivated with thin Al₂O₃ formed by thermal oxidation of evaporated aluminium. Extraction of the small-signal equivalent circuit is also described. Device fabrication involved wet etching of evaporated Al from the Ohmic contact regions prior to metal deposition. This approach yielded an average contact resistance of ∼0.76Ω.mm extracted from transmission line method (TLM) characterisation. Fabricated two-finger AlN/GaN MOS-HEMTs with 0.2µm gate length and 100µm gate width showed good gate control of drain currents up to a gate bias of 3V and achieved a maximum drain current, I_DSmax of ∼1460mA/mm. The peak extrinsic transconductance, G_max, of the device was ∼303mS/mm at V_DS =4V. Current-gain cut-off frequency, f_T, and maximum oscillation frequency, f_MAX, of 50GHz and 40GHz, respectively, were extracted from S-parameter measurements. For longer gate length, L_G =0.5µm, f_T and f_MAX were 20GHz and 30GHz, respectively. These results demonstrate the potential of AlN/GaN MOS-HEMTs for high power and high frequency applications.

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We investigated the effects of various field plate and buried gate structures on the DC and small signal characteristics of 4H-silicon carbide (SiC) metal-semiconductor field-effect transistors (MESFETs). In comparison with the source-connected field plate, the gate-connected field plate exhibited superior frequency response while having similar DC characteristics. In order to further enhance the output power, dual field plates were employed in conjunction with a buried gate structure.

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We fabricated metal-oxide-semiconductor (MOS) devices with Pt/Ta₂O₅ gate stacks and investigated their electrical and structural properties. As increasing RF magnetron sputter-deposition time of Ta₂O₅ film, the values of equivalent oxide thickness (EOT) and flat band voltage (V_FB) increase whilst the density of interfacial trap (D_it) gradually decreases. The effective metal work function (Φ_m,eff) of Pt metal gate, extracted from the relations of EOT versus V_FB are calculated to be ∼5.29eV, implying that Fermi-level pinning in Ta₂O₅ gate dielectric is insignificant.

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In summary, we successfully developed the polymer nonvolatile 4F² memory-cell. It was based on nonvolatile memory characteristics such as memory margin and retention time, which was observed in memory-cell embedded with Ag nanocrystals in PVK layer. The nonvolatile memory characteristics depend on the shape, distribution and isolation of Ag nanocrystals. Accordingly, the thickness of Ag film has an important role in optimizing the Ag nanocrystals. Therefore, the polymer nonvolatile memory-cell is fabricated by appropriate thickness of film and need an improvement of interface between Ag nanocrystals and PVK for sufficient nonvolatile memory characteristics.

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One of the most difficult problems that remains to be solved in wire interconnect architectures is the achievement of lower latency and higher concurrency on a shared bus or link without increasing the power and circuit overhead. Novel improvements in short distance on- and off-chip interconnects can be provided by using a multi-band RF interconnect (RF-I) system. Unlike the conventional current- or voltage-mode square wave signaling transceivers that use binary or multilevel baseband signals, the proposed RF-I transceiver uses high-frequency modulated RF passband signals with binary phase-shift keying (BPSK) modulation. The proposed low-overhead RF-I transceiver using 0.18-µm CMOS technology achieves an aggregate data rate of 4Gb/s/pin between four I/Os (2Tx-to-2Rx) on a shared FR4 PCB line using two carriers of 6GHz and 12GHz. The two transceivers occupy an area of 0.077mm² and dissipate a power of about 25mW with a power efficiency of 6.25pJ/bit.

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A sub-harmonic RF transmitter architecture with simultaneous power combination and carrier-leakage cancellation is proposed. It employs an 8-phase ring-type voltage controlled oscillator (VCO), sub-harmonic mixers, driver amplifiers, and a balun. A signal power is combined with its 180° phase-shifted signal through the balun. Simultaneously carrier-leakage generating in sub-harmonic mixers is canceled by its phase difference. The proposed transmitter achieved 1dBm 1-dB output compression point (P_-1dB) under 1.8V supply and -40dBm carrier-leakage in 5GHz band.

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The fabricated 1.55µm high power superluminescent light emitting diodes (SLEDs) with 115mW maximum output power and 3dB bandwidth of 50nm, using active multi-mode interferometer (MMI), showed high coupling efficiency of 66% into single-mode fiber, which resulted in maximum fiber-coupled power of 77mW.

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This paper presents various types of iterative progressive numerical methods (IPNMs) for the computation of electromagnetic (EM) wave scattering from many objects and reports comparatively the performance of these methods. The original IPNM is similar to the Jacobi method which is one of the classical linear iterative solvers. Then the modified IPNMs are based on other classical solvers like the Gauss-Seidel (GS), the relaxed Jacobi, the successive overrelaxation (SOR), and the symmetric SOR (SSOR) methods. In the original and modified IPNMs, we repeatedly solve linear systems of equations by using a nonstationary iterative solver. An initial guess and a stopping criterion are discussed in order to realize a fast computation. We treat EM wave scattering from 27 perfectly electric conducting (PEC) spheres and evaluate the performance of the IPNMs. However, the SOR- and SSOR-type IPNMs are not subject to the above numerical test in this paper because an optimal relaxation parameter is not possible to determine in advance. The evaluation reveals that the IPNMs converge much faster than a standard BEM computation. The relaxed Jacobi-type IPNM is better than the other types in terms of the net computation time and the application range for the distance between objects.

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We present a design optimization method of H-plane waveguide components, based on the level set method with the finite element method. In this paper, we propose a new formulation for the improvement of a level set function, which describes shape, location, and connectivity of dielectric in a design region. Employing the optimization procedure, we demonstrate that optimized structures of an H-plane waveguide filter and T-junction are obtained from an initial structure composed of several circular blocks of dielectric.

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This paper presents an ultra-wideband amplifier embedded with band-pass filter design. The scattering parameters of a frequency-domain GaAs field effect transistor are converted into z-domain representations by employing the weighted linear least squares method. A least squares scheme is employed to obtain characteristic impedances of transmission line elements that form the amplifier having a flat gain in the passband and good fall-off selectivity in the stopband. Experimental results illustrate the validity of the proposed design method.

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A fifth-order switched-capacitor (SC) complex filter was implemented in 0.2-µm CMOS technology. A novel SC integrator was developed to reduce the die size and current consumption of the filter. The filter is centered at 24.73±0.15kHz (3δ) and has a bandwidth of 20.26±0.3kHz (3δ). The image channel is attenuated by more than 42.6dB. The in-band third-order harmonic input intercept point (IIP3) is 17.3dBm, and the input referred RMS noise is 34.3µV_rms. The complex filter consumes 350µA with a 2.0-V power supply. The die size is 0.578mm². Owing to the new SC integrator, the filter achieves a 27% reduction in die size without any degradation in its characteristics, including its noise performance, compared with the conventional equivalent.

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Motion blur in TFT-LCD is caused by sample and hold characteristic, slow response time of liquid crystal, and the inconsistency between object tracking of the human eye and the actual object location. In order to solve this problem, a high frame rate driving method based on motion estimation and motion compensation has been applied to LCD products. However, as the required processing time of motion estimation increases in LCD TV and monitor systems, real-time video image processing becomes more difficult. Frame interpolation through the large macro block (MB) size has limitations to detect small objects. So, this paper proposes the efficient motion estimator architecture which uses seven kinds of macro blocks to enhance the accuracy of motion estimation and combines the parallel processing with pre-computation technology and hardware optimization for high-speed processing. Also, for increased efficiency in the hardware architecture, we employed an I2C (Inter Integrated Circuit) communication unit to control the key parameters easily through the personnel computer. Simulation results show that the critical path at the motion estimator is reduced by about 27.47% compared to the conventional structure. As a result, the proposed motion estimator will be applicable for the high-speed frame interpolation of variable video.

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Different from distributed baluns, active baluns have group delay variations in the lower bands related to inherent internal capacitances and resistance in transistors. A negative group delay (NGD) circuit is employed as a compensator of group delay variation for an ultra-wideband (UWB) active balun. First, three-cell NGD circuit is inserted into a simple active balun circuit for realizing both group delay compensation and return loss improvement. The simulated results show a group delay variation of 4.8ps and an input return loss of above 11.5dB in the UWB band (3.1-10.6GHz). Then, a pair of one-cell NGD circuits is added to reduce the remaining group delay variation (3.4ps in simulation). The circuit with the NGD circuits was fabricated on an InGaP/GaAs HBT MMIC substrate. The measured results achieved a group delay variation of 7.7ps, a gain variation of 0.5dB, an input return loss of greater than 10dB, and an output return loss of larger than 8.1dB in the UWB band.

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In this paper, a 24GHz frequency source for low phase noise is presented in a 0.18µm CMOS process. The 24GHz frequency source chip is composed of a 12GHz voltage controlled oscillator (VCO) and a 24GHz balanced frequency doubler with class B gate bias. Compared to a conventional complementary VCO, the proposed 12GHz VCO has phase noise improvement by using resistor current sources and substituting the nMOS cross-coupled pair in the conventional complementary VCO for a g_m-boosted nMOS differential Colpitts pair. The measured phase noise and fundamental frequency suppression are -107.17dBc/Hz at a 1MHz offset frequency and -20.95dB at 23.19GHz frequency, respectively. The measured frequency tuning range is from 23.19GHz to 24.76GHz drawing 2.72mA at a supply voltage of 1.8V not including an output buffer.

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CMOS SoCs can reduce power consumption while maintaining performance by adopting voltage scaling (VS) technologies. The operating speed of the level converter (LC) strongly affects the effectiveness of VS technologies. However, PVT variations can cause serious problems to the LC, because the state-of-the-art LC designs do not give enough attention to this issue. In this work, we proposed to analyze the impact of PVT variations on the performance of the LC using a previously developed heuristic sizing methodology. Based on the evaluation results from different operating corners with different offset voltages and temperatures, we proposed a variation-tolerant LC that achieves both high performance and low energy with a high tolerability for PVT variations.

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This paper presents a circuit that improves supply noise rejection using an active inductor circuit. Compared to the conventional designs, the proposed supply noise suppression circuit has better characteristics such as low current consumption and small die size with noise rejection. The circuit was fabricated using 0.13µm UMC CMOS technology. The experimental results showed that the supply noise was suppressed by 61% with only an increase in size of 20.0µm × 2.5µm, and the current consumption was under 2mA.

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