We report on robust and low-power-consumption InP- and GaN-HEMT Low-Noise-Amplifiers (LNAs) operating in Q-band frequency range. A multi-stage common-gate (CG) amplifier with current reuse topology was used. To improve the survivability of the CG amplifier, we introduced a feedback resistor at the gate bias feed. The design technique was adapted to InP- and GaN-HEMT LNAs. The 75nm gate length InP HEMT LNA exhibited a gain of 18dB and a noise figure (NF) of 3dB from 33 to 50GHz. The DC power consumption was 16mW. The Robustness of the InP HEMT LNA was tested by injecting a millimeter-wave input power of 13dBm for 10 minutes. No degradation in a small signal gain was observed. The fabricated 0.12µm gate length GaN HEMT LNA exhibited a gain of 15dB and an NF of 3.2dB from 35 to 42GHz. The DC power consumption was 280mW. The LNA survived until an input power of 28dBm.

In this paper, an accurate experimental noise model to improve the EEHEMT nonlinear model using the Verilog-A language in Agilent ADS is presented for the first time. The present EEHEMT model adopts channel noise to model the noise behavior of pseudomorphic high electron mobility transistor (pHEMT). To enhance the accuracy of the EEHEMT noise model, we add two extra noise sources: gate shot noise and induced gate noise current. Here we demonstrate the power spectral density of the channel noise S_id and gate noise S_ig versus gate-source voltage for 0.25 µm pHEMT devices. Additionally, the related noise source parameters, i.e., P, R, and C are presented. Finally, we compare four noise parameters between the simulation and model, and the agreement between the measurement and simulation results shows that this proposed approach is dependable and accurate.

In general, tunnel diodes exhibit various types of oscillation mode: the sinusoidal mode or the nonsinusoidal mode which is known as the relaxation oscillation (RO) mode. We derive a condition for generating the RO in resonant tunneling diodes (RTDs) with essential components for equivalent circuit model. A conditional equation to obtain sufficient nonlinearity towards the robust RO is clarified. Moreover, its condition also can be applied in case of a bow-tie antenna integrated RTD, thus a design policy to utilize the RO region for the antenna integrated RTD is established by numerical evaluations of time-domain large-signal nonlinear analysis towards a terahertz transmitter for broadband wireless communications.

In this paper, Epitaxial (Epi) Junction Termination Extension (JTE) technique for silicon carbide (SiC) power device is presented. Unlike conventional JTE, the Epi-JTE doesn't require high temperature (about 500°C) implantation process. Thus, it doesn't require high temperature (about 1700°C) process for implanted dose activation and surface defect curing. Therefore, the manufacturing cost will be decreased. Also, the fabrication process is very simple because the dose of the JTE is controlled by epitaxy growth. The blocking characteristic is analyzed through 2D-simulation for the proposed Epi-JTE. In addition, the effect was validated by experiment of fabricated SiC device with the Single-Zone-Epi-JTE. As a result, it has blocking capability of 79.4% compared to ideal parallel-plane junction breakdown.

Improving robustness in electrostatic discharge (ESD) protection by inserting drain-side isolated silicon-controlled rectifiers (SCRs) in a high-voltage (HV) p-channel lateral-diffused MOSFET (pLDMOS) device was investigated in this paper. Additionally, the effects of anti-ESD reliability in the HV pLDMOS transistors provided by this technique were evaluated. From the experimental data, it was determined that the holding voltage (V_h) values of the pLDMOS with an embedded npn-arranged SCR and discrete thin-oxide (OD) layout on the cathode side increased as the parasitic SCR OD row number decreased. Moreover, the trigger voltage (V_t1) and the V_h values of the pLDMOS with a parasitic pnp-arranged SCR and discrete OD layout on the drain side fluctuated slightly as the SCR OD-row number decreased. Furthermore, the secondary breakdown current (I_t2) values (i.e., the equivalent ESD-reliability robustness) of all pLDMOS-SCR npn-arranged types increased (>408.4%) to a higher degree than those of the pure pLDMOS, except for npn-DIS_3 and npn-DIS_2, which had low areas of SCRs. All pLDMOS-SCR pnp-arranged types exhibited an increase of up to 2.2A-2.4A, except for the pnp_DIS_3 and pnp_DIS_2 samples; the pnp_DIS_91 increased by approximately 2000.9% (249.1%), exhibiting a higher increase than that of the reference pLDMOS (i.e., the corresponding pnp-stripe type). The ESD robustness of the pLDMOS-SCR pnp-arranged type and npn-arranged type with a discrete OD layout on the SCR cathode side was greater than that of the corresponding pLDMOS-SCR stripe type and a pure pLDMOS, particularly in the pLDMOS-SCR pnp-arranged type.

The performance of devices based on two dimensional (2D) materials is significantly affected upon prolonged exposure to atmosphere. We analyzed time based environmental degradation of electrical properties of HfS₂ field effect transistors. Atmospheric entities like oxygen and moisture adversely affect the device surface and reduction in drain current is observed over period of 48 hours. Two corrective measures, namely, PMMA passivation and vacuum annealing, have been studied to address the diminution of current by contaminants. PMMA passivation prevents the device from environment and reduces the effect of Coulomb scattering. Improvement in current characteristics signifies the importance of dielectric passivation for 2D materials. On the other hand, vacuum annealing is useful in removing contaminants from the affected surface. In order to figure out optimum process conditions, properties have been studied at various annealing temperatures. The improvement in drain current level was observed upon vacuum annealing within optimum range of annealing temperature.

In this paper, we have investigated the characteristics of PdYb-silicide layer formed by the silicidation of Pd/Yb/n-Si(100) stacked structures for the first time. Pd (12-20 nm)/Yb (0-8 nm) stacked layers were deposited on n-Si(100) substrates by the RF magnetron sputtering at room temperature. Then, 10 nm-thick HfN encapsulating layer was deposited at room temperature. Next, silicidation was carried out by the RTA at 500°C/1 min in N₂ followed by the selective etching. From the J-V characteristics of fabricated Schottky diode, Schottky barrier height (SBH) for electron was reduced from 0.73 eV of Pd₂Si to 0.4 eV of PdYb-silicide in case the Pd/Yb thicknesses were 14/6 nm, respectively.

In this paper, the effect of a nitrogen-doped (N-doped) LaB₆ interfacial layer (IL) on p-type pentacene-based OFET was investigated. The pentacene-based OFET with top-contact/back-gate geometry was fabricated. A 2-nm-thick N-doped LaB₆ interfacial layer deposited on an 8-nm-thick SiO₂ gate insulator. A 10-nm-thick pentacene film was deposited by thermal evaporation at 100°C followed by Au contact and Al back gate electrodes formation. The fabricated OFET showed normally- off characteristics and a steep subthreshold swing (SS) of 84 mV/dec. from I_D-V_G and I_D-V_D characteristics. Furthermore, the aging characteristics of 6 months after the fabrication were investigated and it was found that V_TH and SS were stable when the N-doped LaB₆ IL was introduced at the interface between SiO₂ gate insulator and pentacene.

We have studied the formation of Ti-nanodots (NDs) by remote H₂ plasma (H₂-RP) exposure and investigated how the embedding of Ti-NDs affects the resistive switching properties of Si-rich oxides (SiO_x) because it is expected that NDs will trigger the formation of the conductive filament path in SiO_x. Ti-NDs with an areal density as high as 10¹¹ cm^-2 were fabricated by exposing a Ge/Ti stacked layer to the H₂-RP without external heating, and changes in the chemical structure of Ge/Ti stacked layer with the Ti-NDs formation were evaluated by using hard x-ray photoemission spectroscopy (HAXPES) and x-ray photoelectron spectroscopy (XPS). Resistive switching behaviors of SiO_x with Ti-NDs were measured from current-voltage curves and compared to the results obtained from samples of SiO_x with a Ti thin layer.

Key fabrication technology for the Pt/TiO_2-x/TiO₂/TiO_2+x/Pt nano-film memristor is investigated, including preparing platinum (Pt) electrodes and TiO_2-x/TiO₂/TiO_2+x nano-films. The effect of oxygen flow rate and deposition rate during fabrication on O:Ti ratio of thin films is demonstrated. The fabricated nano-films with different oxygen concentration are validated by the analyzed results from X-ray photoelectron spectroscopy (XPS). The obtained memristor device shows the typical resistive switching behavior and nonvolatile memory effects. An analytical device model for Pt/TiO_2-x/TiO₂/TiO_2+x/Pt nano-film memristor is developed based on the fundamental linear relationships between drift-diffusion velocity and the electric field, and boundary conditions are also incorporated in this model. This model is able to predict the relation between variables in the form of explicit formula, which is very critical in memristor-based circuit designs. The measurement results from real devices validate the proposed analytical device model. Some deviations of the model from the measured data are also analyzed and discussed.

The phonon-drag contribution to the Seebeck coefficient (S_ph) for p-type Si, Ge and Si_1-xGe_x is investigated for thermoelectric applications. The S_ph in Si and Ge is found to mainly determined by the phonon velocity, phonon mean free path and carrier mobility associated with acoustic deformation potential scattering. Moreover, the S_ph in Si_1-xGe_x is predictable by the above-mentioned material parameters interpolated with those in Si and Ge.

The Seebeck coefficient of Si wire co-doped with P and Ga atoms is investigated for applying thermoelectric devices. The observed Seebeck coefficient is closed to the theoretical values of electronic part of Seebeck coefficient due to the electronic transport. From the estimation of phonon scattering processes, it is found that the phonon-drag contribution to the Seebeck coefficient in co-doped Si wire is mainly governed by the phonon-boundary scattering.

We propose a wideband reconfigurable circular-polarized single-port antenna to realize high-density linear integration for use in ground penetrating radars. We switch PIN diodes at a T-shaped probe to change its polarization. The forward- and reverse-biased probes work in cooperation to generate circular polarization. Experiments demonstrate the working bandwidths of 20.0% and 18.6% in the left- and right-hand polarization states, respectively, with 7.2 GHz center frequency. They are wider than those of conventional reconfigurable single-port circular-polarized antennas.

With the scaling of technology, nanoscale CMOS integrated circuits are becoming more sensitive to single event double node upsets induced by charge sharing. A novel highly robust hardened latch design is presented that is fully resilient to single event double node upsets and single node upsets. The proposed latch employs multiple redundant C-elements to form a dual interlocked structure in which the redundant C-elements can bring the affected nodes back to the correct states regardless of the energy of the striking particle. Detailed HSPICE results confirm that the proposed latch features complete resilience to double node upsets and achieves an improved trade-off in terms of robustness, area, delay and power in comparison with previous latches. Extensive Monte Carlo simulations validate the proposed latch features as less sensitive to process, supply voltage and temperature variations.

This paper presents accurate DC and high frequency power-supply rejection (PSR) models for low drop-out (LDO) regulators using different types of active loads and pass transistors. Based on the proposed PSR model, we suggest design guidelines to achieve a high DC PSR or flat bandwidth (BW) by choosing appropriate active loads and pass transistors. Our PSR model captures the intricate interaction between the error amplifiers (EAs) and the pass devices by redefining the transfer function of the LDO topologies. The accuracy of our model has been verified through SPICE simulation and measurements. Moreover, the measurement results of the LDOs fabricated using the 0.18 µm CMOS process are consistent with the design guidelines suggested in this work.