Power consumption has recently emerged as a first class design constraint in system LSI designs. Specially, leakage power has occupied a large part of the total power consumption. Therefore, reduction of leakage power is indispensable for efficient design of high-performance system LSIs. Since 2006, we have carried out a research project called “Innovative Power Control for Ultra Low-Power and High-Performance System LSIs”, supported by Japan Science and Technology Agency as a CREST research program. One of the major objectives of this project is reducing the leakage power consumption of system LSIs by innovative power control through tight cooperation and co-optimization of circuit technology, architecture, and system software designs. In this project, we focused on power gating as a circuit technique for reducing leakage power. Temporal granularity is one of the most important issue in power gating. Thus, we have developed a series of Geysers as proof-of-concept CPUs which provide several mechanisms of fine-grained run-time power gating. In this paper, we describe their concept and design, and explain why co-optimization of different design layers are important. Then, three kinds of power gating implementations and their evaluation are presented from the view point of power saving and temporal granularity.

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Multi-Gate device technology is the promising candidate for the enhancement of device characteristics of the scaled MOSFETs. Moreover, independent-double-gate devices have been proposed to achieve flexible V_th adjustment. It is revealed that the SRAM noise margins have been increased by introducing the independent-double-gate FinFET.

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A motion estimation (ME) multimedia processor was developed by employing dynamic voltage and frequency scaling (DVFS) technique to greatly reduce the power dissipation. To make full use of the advantages of DVFS technique, a fast motion estimation (ME) algorithm was also developed. It can adaptively predict the optimum supply voltage and the optimum clock frequency before ME process starts for each macro-block for encoding. Power dissipation of the 90-nm CMOS DVFS controlled multimedia processor, which contained an absolute difference accumulator as well as a small on-chip DC/DC level converter, a minimum value detector and DVFS controller, was reduced to 38.48µW, which was only 3.261% that of a conventional multimedia processor.

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This paper describes a Histogram of Oriented Gradients (HOG) feature extraction accelerator that features a VLSI-oriented HOG algorithm with early classification in Support Vector Machine (SVM) classification, dual core architecture for parallel feature extraction and multiple object detection, and detection-window-size scalable architecture with reconfigurable MAC array for processing objects of several shapes. To achieve low-power consumption for mobile applications, early classification reduces the amount of computations in SVM classification efficiently with no accuracy degradation. The dual core architecture enables parallel feature extraction in one frame for high-speed or low-power computing and detection of multiple objects simultaneously with low power consumption by HOG feature sharing. Objects of several shapes, a vertically long object, a horizontally long object, and a square object, can be detected because of cooperation between the two cores. The proposed methods provide processing capability for HDTV resolution video (1920×1080 pixels) at 30 frames per second (fps). The test chip, which has been fabricated using 65nm CMOS technology, occupies 4.2×2.1mm² containing 502 Kgates and 1.22Mbit on-chip SRAMs. The simulated data show 99.5mW power consumption at 42.9MHz and 1.1V.

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This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). It features a compression-decoding scheme to reduce the external memory bandwidth for Gaussian Mixture Model (GMM) computation and multi-path Viterbi transition units. We optimize the internal SRAM size using the max-approximation GMM calculation and adjusting the number of look-ahead frames. The test chip, fabricated in 40nm CMOS technology, occupies 1.77mm × 2.18mm containing 2.52 M transistors for logic and 4.29Mbit on-chip memory. The measured results show that our implementation achieves 34.2% required frequency reduction (83.3MHz), 48.5% power consumption reduction (74.14mW) for 60 k-Word real-time continuous speech recognition compared to the previous work while 30% of the area is saved with recognition accuracy of 90.9%. This chip can maximally process 2.4× faster than real-time at 200MHz and 1.1V with power consumption of 168mW. By increasing the beam width, better recognition accuracy (91.45%) can be achieved. In that case, the power consumption for real-time processing is increased to 97.4mW and the max-performance is decreased to 2.08× because of the increased computation workload.

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This paper proposes a novel method to determine a priority for applying selective triple modular redundancy (selective TMR) against single event upset (SEU) to achieve cost-effective reliable implementation of application circuits onto coarse-grained reconfigurable architectures (CGRAs). The priority is determined by an estimation of the vulnerability of each node in the data flow graph (DFG) of the application circuit. The estimation is based on a weighted sum of the node parameters which characterize impact of the SEU in the node on the output data. This method does not require time-consuming placement-and-routing processes, as well as extensive fault simulations for various triplicating patterns, which allows us to identify the set of nodes to be triplicated for minimizing the vulnerability under given area constraint at the early stage of design flow. Therefore, the proposed method enables us efficient design space exploration of reliability-oriented CGRAs and their applications.

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In order to reduce the dynamic energy dissipation in CMOS LSIs, it is effective to reduce the frequency of value changes of the signals. In this paper, a data expression with the valid digit and lower digit overflow information is proposed to suppress unnecessary signal changes in integer functional units and registers of general purpose processors. Experimental results show that the proposed method reduces the energy dissipation by 9.8% for benchmark programs.

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We propose a novel acceleration scheme for Monte Carlo based statistical static timing analysis (MC-SSTA). MC-SSTA, which repeatedly executes ordinary STA using a set of randomly generated gate delay samples, is widely accepted as an accuracy reference. A large number of random samples, however, should be processed to obtain accurate delay distributions, and software implementation of MC-SSTA, therefore, takes an impractically long processing time. In our approach, a generalized hardware module, the STA processing element (STA-PE), is used for the delay evaluation of a logic gate, and netlist-specific information is delivered in the form of instructions from an SRAM. Multiple STA-PEs can be implemented for parallel processing, while a larger netlist can be handled if only a larger SRAM area is available. The proposed scheme is successfully implemented on Altera's Arria II GX EP2AGX125EF35C4 device in which 26 STA-PEs and a 624-port Mersenne Twister-based random number generator run in parallel at a 116MHz clock rate. A speedup of far more than ×10 is achieved compared to conventional methods including GPU implementation.

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This paper proposes an ASIC design support tool set for non-pipelined asynchronous circuits with bundled-data implementation. This tool set consists of seven tools to automate design processes of bundled-data implementation such as the generation of design constraints, timing verification, and delay adjustment considering a given latency constraint. With the proposed design flow which combines the proposed tool set and commercial CAD tools, most of design processes from an RTL model is fully automated. In the experiments, to show the effectiveness of energy consumption in bundled-data implementation compared to synchronous counterpart, this paper synthesizes several circuits with a latency constraint which is generated from the synchronous counterpart with the minimum clock cycle time.

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Three dimensional integration using Through-Silicon Vias (TSVs) offers short inter-layer interconnects and higher packing density. In order to take advantage of these attributes, a novel hybrid 3D NoC-Bus architecture is proposed in the paper. For vertical link, a Fake Token Bus architecture is elaborated, which utilizes the bandwidth efficiently by updating token synchronously. Based on this bus architecture, a methodology of hybrid 3D NoC-Bus design is introduced. The network hybridizes with the bus in vertical link and distributes long links of the full connected network into different layers, which achieves a network with a diameter of only 3 hops and limited radix. In addition, a congestion-aware routing algorithm applied to the hybrid network is proposed. The algorithm routes packets in horizontal firstly when the bus is busy, which balances the communication and reduces the possibility of congestion. Experimental results show that our network can achieve a 34.4% reduction in latency and a 43% reduction in power consumption under uniform random traffic and a 36.9% reduction in latency and a 48% reduction in power consumption under hotspot traffic over regular 3D mesh implementations on average.

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Modern field programmable gate arrays (FPGAs) with heterogeneous resources are partially reconfigurable. Existing methods of reconfiguration-aware floorplanning have limitations with regard to homogeneous resources; they solve only a part of the reconfigurable problem. In this paper, first, a precise model for partially reconfigurable FPGAs is formulated, and then, a two-phase floorplanning approach is presented. In the proposed approach, resource distribution is taken into consideration at all times. In the first step, a resource-aware insertion-after-remove perturbation is devised on the basis of the multi-layer sequence pair constraint graphs, and resource-aware slack-based moves (RASBM) are made to satisfy resource requirements. In the second step, a resource-aware fixed-outline floorplanner is used, and RASBM are applied to pack the reconfigurable regions on the FPGAs. Experimental results show that the proposed approach is resource- and reconfiguration-aware, and facilitates stable floorplanning. In addition, it reduces the wire-length by 4-28% in the first step, and by 12% on average in the second step compared to the wire-length in previous approaches.

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According to the process scaling, radiation-hard devices are becoming sensitive to soft errors caused by Multiple Cell Upset (MCUs). In this paper, the parasitic bipolar effects are utilized to suppress MCUs of the radiation-hard dual-modular flip-flops. Device simulations reveal that a simultaneous flip of redundant latches is suppressed by storing opposite values instead of storing the same value due to its asymmetrical structure. The state of latches becomes a specific value after a particle hit due to the bipolar effects. Spallation neutron irradiation proves that MCUs are effectively suppressed in the D-FF arrays in which adjacent two latches in different FFs store opposite values. The redundant latch structure storing the opposite values is robust to the simultaneous flip.

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In this paper we show that self synchronous circuits can provide robust operation in both soft error prone and low voltage operating environments. Self synchronous circuits are shown to be self checking, where a soft error will either cause a detectable error or halt operation of the circuit. A watchdog circuit is proposed to autonomously detect dual-rail ‘11’ errors and prevent propagation, with measurements in 65nm CMOS showing seamless operation from 1.6V to 0.37V. Compared to a system without the watchdog circuit size and energy-per-operation is increased 6.9% and 16% respectively, while error tolerance to noise is improved 83% and 40% at 1.2V and 0.4V respectively. A circuit that uses the dual-pipeline circuit style as redundancy against permanent faults is also presented and 40nm CMOS measurement results shows correct operation with throughput of 1.2GHz and 810MHz at 1.1V before and after disabling a faulty pipeline stage respectively.

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This paper presents an adaptive cache architecture for wide-range reliable low-voltage operations. The proposed associativity-reconfigurable cache consists of pairs of cache ways so that it can exploit the recovery feature of the novel 7T/14T SRAM cell. Each pair has two operating modes that can be selected based upon the required voltage level of current operating conditions: normal mode for high performance and dependable mode for reliable low-voltage operations. We can obtain reliable low-voltage operations by application of the dependable mode to weaker pairs that cannot operate reliably at low voltages. Meanwhile leaving stronger pairs in the normal mode, we can minimize performance losses. Our chip measurement results show that the proposed cache can trade off its associativity with the minimum operating voltage. Moreover, it can decrease the minimum operating voltage by 140mV achieving 67.48% and 26.70% reduction of the power dissipation and energy per instruction. Processor simulation results show that designing the on-chip caches using the proposed scheme results in 2.95% maximum IPC losses, but it can be chosen various performance levels. Area estimation results show that the proposed cache adds area overhead of 1.61% and 5.49% in 32-KB and 256-KB caches, respectively.

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An effective supply voltage monitor evaluates dynamic variation of (V_dd-V_ss) within power rails of integrated circuits on a die. The monitor occupies an area of as small as 10.8×14.5µm² and is followed by backend digitizing circuits, both using 3.3V thick oxide transistors in a 65nm CMOS technology for covering all power domains from core circuits to peripheral I/O rings. A prototype demonstrates capturing of effective supply voltage waveforms in digital (shift registers) as well as in analog (4bit Flash ADC) circuits.

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We present a small-area second-order all-digital time-to-digital converter (TDC) with two frequency shift oscillators (FSOs) comprising inverter chains and dynamic flipflops featuring low jitter. The proposed FSOs can maintain their phase states through continuous oscillation, unlike conventional gated ring oscillators (GROs) that are affected by transistor leakage. Our proposed FSOTDC is more robust and is eligible for all-digital TDC architectures in recent leaky processes. Low-jitter dynamic flipflops are adopted as a quantization noise propagator (QNP). A frequency mismatch occurring between the two FSOs can be canceled out using a least mean squares (LMS) filter so that second-order noise shaping is possible. In a standard 65-nm CMOS process, an SNDR of 61dB is achievable at an input bandwidth of 500kHz and a sampling rate of 16MHz, where the respective area and power are 700µm² and 281µW.

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In this paper, a robust cyclic ADC architecture with β-encoder is proposed and circuit scheme using switched-capacitor (SC) circuit is introduced. Different from the conventional binary ADC, the redundancy of proposed cyclic ADC outputs β-expansion code and has an advantage of error correction. This feature makes ADC robust against the offset of comparator capacitor mismatch and finite DC gain of amplifier in multiplying-DAC (MDAC). Because the power penalty of high-gain wideband amplifier and the required accuracy of circuit elements for high resolution ADC can be relaxed, the proposed architecture is suitable for deep submicron CMOS technologies beyond 90nm. We also propose a β-value estimation algorithm to realize high accuracy ADC based on β-expansion. The simulation results show the effectiveness of proposed architecture and robustness of β-encoder.

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This paper presents a decoupling capacitance boosting method for the resonant supply noise reduction by fast voltage hopping of DVS systems. The proposed method utilizes a foot transistor as a switch between a conventional decoupling capacitor (decap) and GND. The switching controls of the foot transistor depending on the supply noise states achieve an effective noise reduction as well as fast settling time compared with the conventional passive decaps. The measurement results of a test chip fabricated in a 0.18µm CMOS technology show 12X boost of effective decap value, and 65.8% supply noise reduction with 96% settling time improvement.

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This paper describes the analysis and design of low-noise analog circuits for a new architecture readout LSI, Qpix. In contrast to conventional readout LSIs using TOT method, Qpix measures deposited charge directly as well as time information. A preamplifier with a two-stage op amp and current-copy output buffers is proposed to realize these functions. This preamplifier is configured to implement a charge sensitive amplifier (CSA) and a trans-impedance amplifier (TIA). Design issues related to CSA are analyzed, which includes gain requirement of the op amp, stability and compensation of the two-stage cascode op amp, noise performance estimation, requirement for the resolution of the ADC and time response. The offset calibration method in the TIA to improve the charge detecting sensitivity is also presented. Also, some design principles for these analog circuits are presented. In order to verify the theoretical analysis, a 400-pixel high speed readout LSI: Qpix v.1 has been designed and fabricated in 180nm CMOS process. Calculations and SPICE simulations show that the total output noise is about 0.31mV (rms) at the output of the CSA and the offset voltage is less than 4mV at the output of the TIA. These are attractive performances for experimental particle detector using Qpix v.1 chip as its readout LSI.

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Capacitive feedback VCOs use capacitors that are connected from the output node to the gate of the tail transistor that acts as a current source. Using such feedback results in modulating the current that is used by the oscillator and therefore changes its cyclostationary noise properties which results in a lower output phase noise. This paper presents a mathematical study of capacitive feedback VCOs in terms of stability and phase noise enhancement to confirm stability and to explain the enhancement in phase noise. The derived expression for the phase noise shows an improvement of 4.4dB is achievable by using capacitive feedback as long as the VCO stays in the current limited region. Measurement results taken from an actual capacitive feedback VCO implemented in a 65nm CMOS process also agrees with the analysis and simulation results which further validates the given analysis.

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We propose a compact and high-range resolution 76GHz millimeter-wave radar system for autonomous unmanned helicopters. The purpose of the radar system is to detect and avoid obstacles that may affect the flight safety. To achieve these objectives, a high range resolution and a long detection range are required for the radar systems with small volume and weight. The radar broadband RF front-end module which employs a simple direct conversion method is proposed. The radar module enables the 6GHz RF signal transmission as well as the output power of about 8dBm using commercially available low-cost monolithic microwave integrated circuits. The radar system comprises the broadband RF front-end module, a Ku-band local frequency-modulated continuous wave signal synthesizer, and a very light weight carbon fiber reinforced plastic parabolic reflector antenna. The 5cm of range resolution is experimentally obtained using the 6GHz RF signal bandwidth. The results of the power line measurement confirm an about 23dB signal to noise ratio, which is measured from the reflection of the high-voltage power lines about 150m ahead. In addition, the results of the radar system on-board test using an unmanned helicopter are evaluated. The real-time radar scope, which is transferred through the wireless connection, confirms the detection of the power lines and the other surrounding objects.

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This paper presents a fully differential third-order (2-1) switched-current (SI) cascaded delta-sigma modulator (DSM), with an analog error cancellation logic circuit, and a digital decimation filter that is fabricated using 0.18-µm CMOS technology. The 2-1 architecture with only the quantizer input being fed into the second stage is introduced not only to reduce the circuit complexity, but also to be implemented easily using the switched-current approach. Measurements reveal that the dominant error is the quantization error of the second one-bit quantizer (e₂). This error can be eliminated using an analog error cancellation logic circuit. In the proposed differential sample-and-hold circuit, low input impedance is presented with feedback and width-length adjustment in SI feedback memory cell (FMC); and that a coupled differential replicate (CDR) common-mode feedforward circuit (CMFF) is used to compensate the error of the current mirror. Also, measurements indicate that the signal-to-noise ratio (SNR), dynamic range (DR), effective number of bits (ENOB), power consumption and chip size are 67.3dB, 69dB, 10.9bits, 12.3mW, and 0.20×0.21mm², respectively, with a bandwidth of 40kHz, a sampling rate of 10.24MHz, an OSR of 128 and a supply voltage of 1.8V.

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We present an optimization algorithm for the design of multilayer antireflection (AR) coatings for organic photovoltaic (OPV) cells. When a set of available materials for the AR films is given, the proposed method allows for searching the globally optimized AR structure that maximizes the short-circuit current density (J_SC) under simulated solar light illumination (AM 1.5). By applying this method to an OPV solar cell with a configuration of Al/P3HT:PCBM/MoO₃/ITO, we demonstrated that J_SC can increase by 7.5% with a 6-layer AR coating, consisting of MgF₂, ZnS, and Al₂O₃. A notable feature of this method is that it can find not only the optimal solution, which maximizes J_SC, but also the quasi-optimal solutions, which increase J_SC to nearly maximum levels. We showed that the quasi-optimal solution may have higher robustness against deviations in film thicknesses, from their designated values. This method indicates the importance of practically useful, non-optimal solutions for designing AR coatings. The present method allows for extending the user's choices and facilitates the realization of a practical design for an AR coating.

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A hybrid approach for the synthesis of square thinned arrays with low sidelobes is presented. The proposed method combines the advantages of a genetic algorithm and combinatorial technique-cyclic difference sets (CDSs). The peak sidelobe level (PSL) and the thinning factor are numerically evaluated to show the effectiveness and reliability of the proposed hybrid method. In the proposed GA-enhanced square arrays with the DS and the best CDS, reductions of the PSL, of 4.16dB and 2.45dB, respectively, were achieved as compared to the results of conventional rectangular DS and CDS arrays.

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We describe 25-Gb/s error-free transmission over multi-mode fiber (MMF) by using a transmitter based on a 1.3-µm lens-integrated surface-emitting laser (LISEL) and a CMOS laser-diode driver (LDD). It demonstrates 25-Gb/s error-free transmission over 30-m MMF under the overfilled-launch condition and over 150-m MMF with a power penalty less than 1.0dB under the underfilled-launch condition.

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