The electric properties of a field-effect transistor not only depend on gate surface sidewall but also on channel orientation when applying channel stain engineering. The change of the gate surface and channel orientation through the rotated FinFETs provides the capability to compare the orientation dependence of performance and reliability. This study characterized the <100> and <110> channels of FinFETs on the same wafer under tensile and compressive stresses by cutting the wafer into rectangular silicon pieces and evaluated their piezoresistance coefficients. The piezoresistance coefficients of the <100> and <110> silicon under tensile and compressive stresses were first evaluated based on the current setup. Tensile stresses enhance the mobilities of both <100> and <110> channels, whereas compressive stresses degrade them. Electrical characterization revealed that the threshold voltage variation and drive current degradation of the {100} surface were significantly higher than those of {110} for positive bias temperature instability and hot carrier injection with equal gate and drain voltage (V_G=V_D). By contrast, insignificant difference is noted for the subthreshold slope degradation. These findings imply that a higher ratio of bulk defect trapping is generated by gate voltage on the <100> surface than that on the <110> surface.

We have investigated post-metallization annealing (PMA) utilizing TiN gate electrode on the thin ferroelectric undoped HfO₂ directly deposited on p-Si(100) by RF magnetron sputtering. By post-deposition annealing (PDA) process at 600^°C/30 s in N₂, the memory window (MW) in the C-V characteristics was observed in the Al/HfO₂/p-Si(100) diodes with 15 to 24-nm-thick HfO₂. However, it was not obtained when the thickness of HfO₂ was 10 nm. On the other hand, the MW was observed for Pt/TiN/HfO₂ (10 nm)/p-Si(100) diodes utilizing PMA process at 600^°C/30 s. The MW was 0.5 V when the bias voltage was applied from -3 to 3 V.

For the further scaling and lower voltage applications of nonvolatile ferroelectric memory, the effect of Kr/O₂ sputtering for SrBi₂Ta₂O₉ (SBT) thin film formation was investigated utilizing a SrBi₂Ta₂O₉ target. The 80-nm-thick SBT films were deposited by radio-frequency (RF) magnetron sputtering on Pt/Ti/SiO₂/Si(100). Compared with Ar/O₂ sputtering, the ferroelectric properties such as larger remnant polarization (Pr) of 3.2 µC/cm² were observed with decrease of leakage current in case of Kr/O₂ sputtering. X-ray diffraction (XRD) patterns indicated that improvement of the crystallinity with suppressing pyrochlore phases and enhancing ferroelectric phases was realized by Kr/O₂ sputtering.

We investigated the low temperature formation of Pd₂Si on Si(100) with TiN encapsulating layer formed at 500^°C/1 min. Furthermore, the dopant segregation process was performed with ion dose of 1x10¹⁵ cm^-2 for B⁺. The uniform Pd₂Si was successfully formed with low sheet resistance of 10.4 Ω/sq. Meanwhile, the PtSi formed on Si(100) showed rough surface morphology if the silicidation temperature was 500^°C. The estimated Schottky barrier height to hole of 0.20 eV (qφ_Bp) was realized for n-Si(100).

In this paper, we have investigated the etching selectivity of HfN encapsulating layer for high quality PtHf-alloy silicide (PtHfSi) formation with low contact resistivity on Si(100). The HfN(10 nm)/PtHf(20 nm)/p-Si(100) stacked layer was in-situ deposited by RF-magnetron sputtering at room temperature. Then, silicidation was carried out at 500^°C/20 min in N₂/4.9%H₂ ambient. Next, the HfN encapsulating layer was etched for 1-10 min by buffered-HF (BHF) followed by the unreacted PtHf metal etching. We have found that the etching duration of the 10-nm-thick HfN encapsulating layer should be shorter than 6 min to maintain the PtHfSi crystallinity. This is probably because the PtHf-alloy silicide was gradually etched by BHF especially for the Hf atoms after the HfN was completely removed. The optimized etching process realized the ultra-low contact resistivity of PtHfSi to p⁺/n-Si(100) and n⁺/p-Si(100) such as 9.4×10^-9Ωcm² and 4.8×10^-9Ωcm², respectively, utilizing the dopant segregation process. The control of etching duration of HfN encapsulating layer is important to realize the high quality PtHfSi formation with low contact resistivity.

We have fabricated multiple-stacked Si quantum dots (QDs) with and without Ge core embedded in a SiO₂ network on n-Si(100) and studied their field electron emission characteristics under DC bias application. For the case of pure Si-QD stacks with different dot-stack numbers, the average electric field in dot-stacked structures at which electron emission current appeared reached minimum value at a stack number of 11. This can be attributed to optimization of the electron emission due to enhanced electric field concentration in the upper layers of the dot-stacked structures and reduction of the electron injection current from the n-Si substrate, with an increased stack number. We also found that, by introducing Ge core into Si-QDs, the average electric field for the electron emission can be reduced below that from pure Si-QDs-stacked structures. This result implies that the electric field is more concentrated in the upper Si-QDs with Ge core layers due to deep potential well for holes in the Ge core.

We fabricate and characterize a GaAsSb/InGaAs backward diode (BWD) toward a realization of high sensitivity zero bias microwave rectification for RF wave energy harvest. Lattice-matched p-GaAsSb/n-InGaAs BWDs were fabricated and their current-voltage (I-V) characteristics and S-parameters up to 67 GHz were measured with respect to several sorts of mesa diameters in µm order. Our theoretical model and analysis are well fitted to the measured I-Vs on the basis of WKB approximation of the transmittance. It is confirmed that the interband tunneling due to the heterojunction is a dominant transport mechanism to exhibit the nonlinear I-V around zero bias regime unlike recombination or diffusion current components on p-n junction contribute in large current regime. An equivalent circuit model of the BWD is clarified by confirming theoretical fitting for frequency dependent admittance up to 67 GHz. From the circuit model, eliminating the parasitic inductance component, the frequency dependence of voltage sensitivity of the BWD rectifier is derived with respect to several size of mesa diameter. It quantitatively suggests an effectiveness of mesa size reduction to enhance the intrinsic matched voltage sensitivity with increasing junction resistance and keeping the magnitude of I-V curvature coefficient.

We numerically demonstrate a possibility on-off keying (OOK) type of modulation over tens gigabits per second for sub-terahertz radiation in our proposed wireless transmitter device structure towards radio over fiber (RoF) technology. The integrated device consists of an InP-based compound semiconductor resonant tunneling diode (RTD) adjacent to an InP-based photo diode (PD), a self-complementary type of bow-tie antenna (BTA), external microstrip lines. These integration structures are carefully designed to obtain robust relaxation oscillation (RO) due to the negative differential conductance (NDC) characteristic of the RTD and the nonlinearity of the NDC. Moreover, the device is designed to exhibit OOK modulation of RO due to photo current from the PD inject into the RTD. Electromagnetic simulations and nonlinear equivalent circuit model of the whole device structure are established to perform large signal analysis numerically with considerations of previously measured characteristics of the triple-barrier RTD.

Hydrophobic DNA (H-DNA) nano-film was formed as the surface modifier on a thin glass plate working as a slab optical waveguide (SOWF). Cytochrom c (cytc) molecules were immobilized from aqueous solution with direct contacting to the H-DNA nano-film for 30 minutes. From SOWG absorption spectral changes during automated solution exchange (SE) processes, it was found that about 28.1% of cytc molecules was immobilized in the H-DNA nano-film with keeping their reduction functionality by reducing reagent.

In order to optimize the performance of thermoelectric devices, we have fabricated and characterized the micrometer-scaled Si thermopile preserving the phonon-drag effect, where the Si thermopile consists of p- and n-type Si wire pairs. The measured Seebeck coefficient of the p-type Si wire was found to be higher than the theoretical value calculated only from the carrier transport, which indicates the contribution of phonon-drag part. Moreover, the measured Seebeck coefficient increased with increasing the width of Si wire. This fact is considered due to dependency of phonon-drag part on the wire width originating from the reduction of phonon-boundary scattering. These contributions were observed also in measured output voltage of Si-wire thermopile. Hence, the output voltage of Si-wire thermopile is expected can be enhanced by utilizing the phonon-drag effect in Si wire by optimizing its size and carrier concentration.

In this paper, we propose a new technique for the transient scattering problem of periodically arrayed dispersion media for the TE case by using a combination of the Fourier series expansion method (FSEM) and the fast inversion Laplace transform (FILT) method, and analyze the pulse response for various widths of the dispersion media. As a result, we clarified the influence of the dispersion media with an air region on the resulting waveform.

This report focuses on an optimization scheme of advanced MOSFETs for designing CMOS circuits with high power efficiency. For this purpose the physics-based compact model HiSIM2 is applied so that the relationship between device and circuit characteristics can be investigated properly. It is demonstrated that the short-channel effect, which is usually measured by the threshold-voltage shift relative to long-channel MOSFETs, provides a consistent measure for device-performance degradation with reduced channel length. However, performance degradations of CMOS circuits such as the power loss cannot be predicted by the threshold-voltage shift alone. Here, the subthreshold swing is identified as an additional important measure for power-efficient CMOS circuit design. The increase of the subthreshold swing is verified to become obvious when the threshold-voltage shift is larger than 0.15V.

A multi-carrier and blind shift-frequency jamming(MCBSFJ) against the pulsed compression radar with order-statistic (OS) constant false alarm rate (CFAR) detector is proposed. Firstly, according to the detection principle of the OS-CFAR detector, the design requirements for jamming signals are proposed. Then, some key parameters of the jamming are derived based on the characteristics of the OS-CFAR detector. As a result, multiple false targets around the real target with the quantity, amplitude and space distribution which can be controlled are produced. The simulation results show that the jamming method can reduce the detection probability of the target effectively.