Embedded system approaches to edge computing in IoT implementations are proposed and discussed. Rationales of edge computing and essential core capabilities for IoT data supply innovation are identified. Then, innovative roles and development of MCU and embedded flash memory are illustrated by technology and applications, expanding from CPS to big-data and nomadic/autonomous elements of IoT requirements. Conclusively, a technology roadmap construction specific to IoT is proposed.

Cross sections that cause single event upsets by heavy ions are sensitive to doping concentration in the source and drain regions, and the structure of the raised source and drain regions especially in FDSOI. Due to the parasitic bipolar effect (PBE), radiation-hardened flip flops with stacked transistors in FDSOI tend to have soft errors, which is consistent with measurement results by heavy-ion irradiation. Device-simulation results in this study show that the cross section is proportional to the silicon thickness of the raised layer and inversely proportional to the doping concentration in the drain. Increasing the doping concentration in the source and drain region enhance the Auger recombination of carriers there and suppresses the parasitic bipolar effect. PBE is also suppressed by decreasing the silicon thickness of the raised layer. C_gg-V_gs and I_ds-V_gs characteristics change smaller than soft error tolerance change. Soft error tolerance can be effectively optimized by using these two determinants with only a small impact on transistor characteristics.

This paper presents a 28-GHz-band highly linear stacked-FET power amplifier (PA) IC. A 4-stacked-FET structure is employed for high output power considering the low breakdown voltage of scaled MOSFET transistors. A novel adaptive bias circuit is proposed to dynamically control the gate-to-source bias voltage for amplification MOSFETs. The novel adaptive bias allows the PA to attain high linearity with high back-off efficiency. In addition, the third-order intermodulation distortion (IM3) is improved by a multi-cascode structure. The PA IC is designed, fabricated and fully tested in 56-nm SOI CMOS technology. At a supply voltage of 4 V, the PA IC has achieved an output power of 20.0 dBm with a PAE as high as 38.1% at the 1-dB gain compression point (P1dB). Moreover, PAEs at 3-dB and 6-dB back-off from P1dB are 36.2% and 28.7%, respectively. The PA IC exhibits an output third-order intercept point (OIP3) of 25.0 dBm.

This paper analyzes the system-level performance of Storage Class Memory (SCM)/NAND flash hybrid solid-state drives (SSDs) and SCM/NAND flash/NAND flash tri-hybrid SSDs in difference types of NAND flash memory. There are several types of NAND flash memory, i.e. 2-dimensional (2D) or 3-dimensional (3D), charge-trap type (CT) and floating-gate type (FG) and multi-level cell (MLC) or triple-level cell (TLC). In this paper, the following four types of NAND flash memory are analyzed: 1) 3D CT TLC, 2) 3D FG TLC, 3) 2D FG TLC, and 4) 2D FG MLC NAND flash. Regardless of read- and write-intensive workloads, SCM/NAND flash hybrid SSD with low cost 3D CT TLC NAND flash achieves the best performance that is 20% higher than that with higher cost 2D FG MLC NAND flash. The performance improvement of 3D CT TLC NAND flash can be obtained by the short write latency. On the other hand, in case of tri-hybrid SSD, SCM/3D CT TLC/3D CT TLC NAND flash tri-hybrid SSD improves the performance 102% compared to SCM/2D FG MLC/3D CT TLC NAND flash tri-hybrid SSD. In addition, SCM/2D FG MLC/2D FG MLC NAND flash tri-hybrid SSD shows 49% lower performance than SCM/2D FG MLC/3D CT TLC NAND flash tri-hybrid SSD. Tri-hybrid SSD flash with 3D CT TLC NAND flash is the best performance in tri-hybrid SSD thanks to larger block size and word-line (WL) write. Therefore, in 3D CT TLC NAND flash based SSDs, higher cost MLC NAND flash is not necessary for hybrid SSD and tri-hybrid SSD for data center applications.

This paper analyzes the optimal SSD configuration including emerging non-volatile memories such as quadruple-level cell (QLC) NAND flash memory [1] and storage class memories (SCMs). First, SSD performance and SSD endurance lifetime of hybrid SSD are evaluated in four configurations: 1) single-level cell (SLC)/QLC NAND flash, 2) SCM/QLC NAND flash, 3) SCM/triple-level cell (TLC)/QLC NAND flash and 4) SCM/TLC NAND flash. Furthermore, these four configurations are compared in limited cost. In case of cold workloads or high total SSD cost assumption, SCM/TLC NAND flash hybrid configuration is recommended in both SSD performance and endurance lifetime. For hot workloads with low total SSD cost assumption, however, SLC/QLC NAND flash hybrid configuration is recommended with emphasis on SSD endurance lifetime. Under the same conditions as above, SCM/TLC/QLC NAND flash tri-hybrid is the best configuration in SSD performance considering cost. In particular, for prxy_0 (write-hot workload), SCM/TLC/QLC NAND flash tri-hybrid achieves 67% higher IOPS/cost than SCM/TLC NAND flash hybrid. Moreover, the configurations with the highest IOPS/cost in each workload and cost limit are picked up and analyzed with various types of SCMs. For all cases except for the case of prxy_1 with high total SSD cost assumption, middle-end SCM (write latency: 1us, read latency: 1us) is recommended in performance considering cost. However, for prxy_1 (read-hot workload) with high total SSD cost assumption, high-end SCM (write latency: 100ns, read latency: 100ns) achieves the best performance.

Double modular redundancy (DMR) is to execute operations twice and detect soft error by comparing the operation results. The error is corrected by executing necessary operations again. For the DMR design of conditional processing, a method is proposed which makes the secondary executions of the duplicated operations be dependent on the primary execution of the condition operation, thereby widening the schedule solution space and allowing better results to be derived. The energy minimization with the proposed method is formulated as ILP models and the optimum solution is obtained by using an ILP solver.

TCAD simulation was performed to investigate the material properties of an AlGaN/GaN structure in Deep Acceptor (DA)-rich and Deep Donor (DD)-rich GaN cases. DD-rich semi-insulating GaN generated a positively charged area thereof to prevent the electron concentration in 2DEG from decreasing, while a DA-rich counterpart caused electron depletion, which was the origin of the current collapse in AlGaN/GaN HFETs. These simulation results were well verified experimentally using three nitride samples including buffer-GaN layers with carbon concentration ([C]) of 5×10¹⁷, 5×10¹⁸, and 4×10¹⁹ cm^-3. DD-rich behaviors were observed for the sample with [C]=4×10¹⁹ cm^-3, and DD energy level E_DD=0.6 eV was estimated by the Arrhenius plot of temperature-dependent I_DS. This E_DD value coincided with the previously estimated E_DD. The backgate experiments revealed that these DD-rich semi-insulating GaN suppressed both current collapse and buffer leakage, thus providing characteristics desirable for practical usage.

In partially depleted SOI (PD-SOI) technology, the SCR-based protection device is desired due to its relatively high robustness, but be restricted to use because of its inherent low holding voltage (V_h) and high triggering voltage (V_t1). In this paper, the body-tie side triggering diode inserting silicon controlled rectifier (BSTDISCR) is proposed and verified in 180 nm PD-SOI technology. Compared to the other devices in the same process and other related works, the BSTDISCR presents as a robust and latchup-immune PD-SOI ESD protection device, with appropriate V_t1 of 6.3 V, high V_h of 4.2 V, high normalized second breakdown current (I_t2), which indicates the ESD protection robustness, of 13.3 mA/µm, low normalized parasitic capacitance of 0.74 fF/µm.

For the RF power amplifier, its exposed input and output are susceptible to damage from Electrostatic (ESD) damage. The bi-direction protection is required at the input in push-pull operating mode. In this paper, considering the process compatibility to the power amplifier, cascaded Grounded-gate NMOS (ggNMOS) and Polysilicon diodes (PDIO) are stacked together to form an ESD clamp with forward and reverse protection. Through Transmission line pulse (TLP) and CV measurements, the clamp is demonstrated as latch-up immune and low parasitic capacitance bi-direction ESD protection, with 18.67/17.34V holding voltage (V_hold), 4.6/3.2kV ESD protection voltage (V_ESD), 0.401/0.415pF parasitic capacitance (C_ESD) on forward and reverse direction, respectively.