We review our recent achievements in monolithic 3D-ICs and flexible electronics based on single-grain Si TFTs that are fabricated inside a single-grain with a low-temperature process. Based on pulsed-laser crystallization and submicron sized cavities made in the substrate, amorphous-Si precursor film was converted into poly-Si having grains that are formed on predetermined positions. Using the method called µ-Czochralski process and LPCVD a-Si precursor film, two layers of the SG Si TFT layers with the grains having a diameter of 6µm were vertically stacked with a maximum process temperature of 550°C. Mobility for electrons and holes were 600cm²/Vs and 200cm²/Vs, respectively. As a demonstration of monolithic 3D-ICs, the two SG-TFT layers were successfully implemented into CMOS inverter, 3D 6T-SRAM and single-grain lateral PIN photo-diode with in-pixel amplifier. The SG Si TFTs were applied to flexible electronics. In this case, the a-Si precursor was prepared by doctor-blade coating of liquid-Si based on pure cyclopentasilane (CPS) on a polyimide (PI) substrate with maximum process temperature of 350°C. The µ-Czochralski process provided location-controlled Si grains with a diameter of 3µm and mobilities of 460 and 121cm²/Vs for electrons and holes, respectively, were obtained. The devices on PI were transferred to a plastic foil which can operate with a bending diameter of 6mm. Those results indicate that the SG TFTs are attractive for their use in both monolithic 3D-ICs and flexible electronics.

View full abstract

This paper discusses Mixed Signal LSI technology with embedded power transistors. Trends in Mixed Signal LSI technology are explained at first. Mixed signal LSI technology has proceeded with the help of fine fabrication technology and SOI technology. The BEOL transistor is a new development, which uses InGaZnO (IGZO) as its TFT channel material. The BEOL transistor is one future device which enables 3D IC and chip shrinking technology.

View full abstract

A photovoltaic (PV)-assisted CMOS rectifier was developed for efficient energy harvesting from ambient radio waves as one example of the synergistic energy harvesting concept. The rectifier operates truly synergistically. A pn junction diode acting as a PV cell converts light energy to DC bias voltage, which compensates the threshold voltage (Vth) of the MOSFETs and enhances the radio frequency (RF) to DC power conversion efficiency (PCE) of the rectifier even under extremely low input power conditions. The indoor illuminance level was sufficient to generate gate bias voltages to compensate Vths. Although the same PV cell structure for biasing nMOS and pMOS transistors was used, photo-generated bias voltages were found to become unbalanced due to the two-layered pn junction structures and parasitic bipolar transistor action. Under typical indoor lighting conditions, a fabricated PV-assisted rectifier achieved a PCE greater than 20% at an RF input power of -20dBm, a frequency of 920MHz, and an output load of 47kΩ. This PCE value is twice the value obtained by a conventional rectifier without PV assistance. In addition, it was experimentally revealed that if symmetric biasing voltages for nMOS and pMOS transistors were available, the PCE would increase even further.

View full abstract

A modern system-on-chip (SoC) includes many heterogeneous IP components. Generally, a few embedded processors are integrated into SoCs. An asynchronous circuit design technique is employed to achieve low power/energy consumption. In this paper, we design an asynchronous embedded processor on FPGAs and analyze its possible benefits on commercial FPGAs. We use commercially available 65nm high-performance Virtex-5 and 45nm low-power Spartan-6 Xilinx FPGAs to show the impact on power consumption for the two different extreme cases. For the high performance Virtex-5, our asynchronous processor shows 36.8% lower power consumption when compared with its synchronous counterpart. On the other hand, the asynchronous processor consumes 25.6% more power in a low power Spartan-6 FPGA. However, through simple analysis and power simulation, we show that the event-driven nature of asynchronous circuits can further save power/energy even in the Spartan-6 FPGA.

View full abstract

An LSI Chip-Package-Board integrated power noise simulation model and its validity is discussed in this paper. A unified power delivery network (PDN) of LSI chip, package, and printed circuit board (PCB) is connected with on-chip power supply current models with capacitor charging expression. The proposed modeling flow is demonstrated for the 32-bit microprocessor in a 1.0V 90nm CMOS technology. The PDN of the system that includes a chip, bonding wires and a printed circuit board is modeled in an equivalent circuit. The on-chip power supply noise monitoring technique and the magnetic probe method is applied for validating simulation results. Simulations and measurements explore power supply noise generation with the dependency on operating frequencies in the wide range from 10MHz to 300MHz, under the operation mode of dynamic frequency scaling, and in the long time operation with various operation codes. It is confirmed that the proposed power supply noise simulation model is helpful for the noise estimation throughout the design phase of the LSI system.

View full abstract

Power supply noise waveforms within cryptographic VLSI circuits in a 65nm CMOS technology are captured by using an on-chip voltage waveform monitor (OCM). The waveforms exhibit the correlation of dynamic voltage drops to internal logical activities during Advance Encryption Standard (AES) processing, and causes side-channel information leakage regarding to secret key bytes. Correlation Power Analysis (CPA) is the method of an attack extracting such information leakage from the waveforms. The frequency components of power supply noise contributing the leakage are shown to be localized in an extremely low frequency region. The level of information leakage is strongly associated with the size of increment of dynamic voltage drops against the Hamming distance in the AES processing. The time window of significant importance where the leakage most likely happens is clearly designated within a single clock cycle in the final stage of AES processing. The on-chip power supply noise measurements unveil the facts about side-channel information leakage behind the traditional CPA with on-board sensing of power supply current through a resistor of 1 ohm.

View full abstract

This paper proposes a novel and an efficient method termed hypersphere sampling to estimate the circuit yield of low-failure probability with a large number of variable sources. Importance sampling using a mean-shift Gaussian mixture distribution as an alternative distribution is used for yield estimation. Further, the proposed method is used to determine the shift locations of the Gaussian distributions. This method involves the bisection of cones whose bases are part of the hyperspheres, in order to locate probabilistically important regions of failure; the determination of these regions accelerates the convergence speed of importance sampling. Clustering of the failure samples determines the required number of Gaussian distributions. Successful static random access memory (SRAM) yield estimations of 6- to 24-dimensional problems are presented. The number of Monte Carlo trials has been reduced by 2-5 orders of magnitude as compared to conventional Monte Carlo simulation methods.

View full abstract

A high-speed and low-power 8-bit subranging analog-to-digital converter (ADC) based on 65-nm CMOS technology was fabricated. Rather than using digital foreground calibration, an analog-centric approach was adopted to reduce power dissipation. An offset cancelling charge-steering amplifier and capacitive-averaging technique effectively reduce the offset, noise, and power dissipation of the ADC. Moreover, the circuit used to compensate the kickback noise current from the comparator can also reduce the power dissipation. The reference-voltage generator for the fine ADC is composed of a fine ladder and a capacitor providing an AC signal path. This configuration reduces the power dissipation of the selection signal drivers for the analog multiplexer. A test chip fabricated using 65-nm digital CMOS technology achieved a high sampling rate of 1GHz, a low power dissipation of 17.5mW, and a figure of merit of 118fJ/conv.-step.

View full abstract

A 7bit 1GS/s flash ADC using two bit active interpolation and background offset calibration is proposed and tested. It achieves background calibration using 36 pre-amplifiers with 139 comparators. To cancel the offset, two pre-amplifiers and 12 comparators are set to offline in turn while the others are operating. A two bit active interpolation design and an offset cancellation scheme are implemented in the latch stage. The interpolation and background calibration significantly reduce analog input signal as well as reference voltage load. Fabricated with the 90nm CMOS process, the proposed ADC consumes 95mW under a 1.2V power supply.

View full abstract

Proof-of-concept cyclic analog-to-digital converters (ADCs) have been designed and fabricated in 90-nm CMOS technology. The measurement results of an experimental prototype demonstrate the effectiveness of the proposed switched-capacitor (SC) architecture to realize a non-binary ADC based on β expansion. Different from the conventional binary ADC, a simple 1-bit/step structure for an SC multiplying digital-to-analog converter (MDAC) is proposed to present residue amplification by β (1 < β < 2). The redundancy of non-binary ADCs with radix β tolerates the non-linear conversion errors caused by the offsets of comparators, the mismatches of capacitors, and the finite DC gains of amplifiers, which are used in the MDAC. We also employed a radix value estimation algorithm to obtain an effective value of β for non-binary encoding; it can be realized by merely adding a simple conversion sequence and digital circuits. As a result, the power penalty of a high-gain wideband amplifier and the required accuracy of the circuit elements for a high-resolution ADC were largely relaxed so that the circuit design was greatly simplified. The implemented ADC achieves a measured peak signal-to-noise-and-distortion-ratio (SNDR) of 60.44dB, even with an op-amp with a poor DC gain (< 50dB) while dissipating 780µW in analog circuits at 1.4V and occupying an active area of 0.25 × 0.26mm².

View full abstract

This paper derives a maximum lock range of an injection locked ring oscillator in a direct injection method and presents an injection locked charge-pump phase-locked loop (CPPLL) with a replica of a ring oscillator. The proposed injection-locked PLL separates the injection-locked VCO from the continuous phase-tracking loop of the PLL such that can provide stable lock-state maintenance and tolerance to temperature and supply voltage variation. The measurement results show that the proposed injection-locked PLL can be tolerable to voltage variation of 11.2% in supply voltage of 1.2V. In-band noises of the injection-locked oscillator at offset frequencies of 10kHz and 100kHz are -108.2dBc/Hz and -114.6dBc/Hz, respectively.

View full abstract

This paper proposes a radiation-hardened phase-locked loop (RH-PLL) with a switchable dual modular redundancy (DMR) structure. After radiation strikes, unhardened PLLs suffer clock perturbations. Conventional RH-PLLs have been proposed to reduce recovery time after perturbation. However, this recovery still requires tens of clock cycles. Our proposal involves ‘detecting’ and ‘switching’, rather than ‘recovering’ from clock perturbation. Detection speed is crucial for robust perturbation-immunity. We identify types of clock perturbation and then propose a set of detectors to detect each type. With this method, the detectors guarantee high-speed detection that leads to perturbation-immune switching from a radiated clock to an undistorted clock. The proposed RH-PLL was fabricated and then verified with a radiation test on real silicon.

View full abstract

This paper presents a resilient cache memory for dynamic variation tolerance in a 40-nm CMOS. The cache can perform sustained operations under a large-amplitude voltage droop. To realize sustained operation, the resilient cache exploits 7T/14T bit-enhancing SRAM and on-chip voltage/temperature monitoring circuit. 7T/14T bit-enhancing SRAM can reconfigure itself dynamically to a reliable bit-enhancing mode. The on-chip voltage/temperature monitoring circuit can sense a precise supply voltage level of a power rail of the cache. The proposed cache can dynamically change its operation mode using the voltage/temperature monitoring result and can operate reliably under a large-amplitude voltage droop. Experimental result shows that it does not fail with 25% and 30% droop of V_dd and it provides 91 times better failure rate with a 35% droop of V_dd compared with the conventional design.

View full abstract

This paper gives a write voltage and read reference current generator considering temperature characteristics for multi-level Ge₂Sb₂Te₅-based phase change memories. Since the optimum SET and RESET voltages linearly changes by the temperature, the voltage supply circuit must track this characteristic. In addition, the measurement results show that the read current depends on both read temperature and the write temperature and has exponential dependence on the read temperature. Thus, the binning technique is applied for each read and write temperature regions. The proposed variable TC generator can achieve below ±0.5 LSB precision from the measured differential non-linearity and integral non-linearity. As a result, the temperature characteristics of both the linear write voltage and the exponential read current can be tracked with the proposed variation tolerant linear temperature coefficient current generator.

View full abstract

In this paper, we propose an optimum access method for a phase change memory (PCM) with NAND strings. A PCM with a block erase interface is proposed. The method, which has a SET block erase operation and fast RESET programming, is proposed since the SET operation causes a slow access time for conventional PCM;. From the results of measurement, the SET-ERASE operation is successfully completed while the RESET-ERASE operation is incomplete owing to serial connection. As a result, the block erase interface with the SET-ERASE and RESET program method realizes a 7.7 times faster write speed compared than a conventional RAM interface owing to the long SET time. We also give pass-transistor design guidelines for PCM with NAND strings. In addition, the write-capability and write-disturb problems are investigated. The ERASE operation for the proposed device structure can be realized with the same current as that for the SET operation of a single cell. For the pass transistor, about 4.4 times larger on-current is needed to carry out the RESET operation and to avoid the write-disturb problem than the minimum RESET current of a single cell. In this paper, the SET programming method is also verified for a conventional RAM interface. The experimental results show that the write-capability and write-disturb problems are negligible.

View full abstract

New media processing applications such as image recognition and AR (Augment Reality) have become into practical on embedded systems for automotive, digital-consumer and mobile products. Many-core processors have been proposed to realize much higher performance than multi-core processors. We have developed a low-power many-core SoC for multimedia applications in 40nm CMOS technology. Within a 210mm² die, two 32-core clusters are integrated with dynamically reconfigurable processors, hardware accelerators, 2-channel DDR3 I/Fs, and other peripherals. Processor cores in the cluster share a 2MB L2 cache connected through a tree-based Network-on-Chip (NoC). Its total peak performance exceeds 1.5TOPS (Tera Operations Per Second). The high scalability and low power consumption are accomplished by parallelized software for multimedia applications. In case of face detection, the performance scales up to 64 cores and the SoC consumes only 2.21W. Moreover, it can execute the 1080p 48fps H.264 decoding about 520mW by 28 cores and the 4K2K 15fps super resolution about 770mW by 32 cores in one cluster. Exploiting parallelism by low power processor cores, the many-core SoC provides several tens of times better energy efficiency than that of a high performance desk-top quad-core processor.

View full abstract

We numerically investigated the optical output characteristics in two kinds of optical waveguide coupled high-index-contrast subwavelength grating VCSELs (HCG-VCSELs) that couple the laser output to the in-plane waveguide, operating at a 1.55-µm region. One is the transverse electric (TE) HCG, and the other is the transverse magnetic (TM) HCG. In a waveguide coupled HCG without a cavity structure, the out-coupling efficiency to the waveguide strongly depends on the intensity of the incident light at the starting edge of the waveguide. In a waveguide coupled HCG-VCSEL, the ratio of the waveguide output to the optical power inside the active region is determined also by the intensity of the resonant mode at the waveguide edge. The TE-HCG-VCSEL exhibited an almost 30 times larger waveguide output power while the quality factor of the laser cavity is 1/3, compared to those in the TM-HCG-VCSEL. The single mode condition was satisfied for the waveguide of the TE-HCG-VCSEL while the first order mode was allowed for that of the TM-HCG-VCSEL. Positioning the mesa edge at the waveguide edge within 1-µm accuracy results in waveguide outputs of about 0.7 and 0.02% of that inside the active region for TE- and TM-HCG-VCSEL, respectively.

View full abstract

A new digital controller for a single-phase boost power factor correction (PFC) converter operating at a discontinuous conduction mode (DCM), is presented to achieve high input power factor over wide input voltage and load range. A method of duty cycle modulation is proposed to reduce the line harmonic distortion and improve the power factor. The loop regulation scheme is adopted to further improve the system stability and the power factor simultaneously. Meanwhile, a novel digital pulse width modulator (DPWM) based on the delay lock loop technique, is realized to improve the regulation linearity of duty cycle and reduce the regulation deviation. The single-phase DCM boost PFC converter with the proposed digital controller based on the field programmable gate array (FPGA) has been implemented. Experimental results indicate that the proposed digital controller can achieve high power factor more than 0.99 over wide input voltage and load range, the output voltage deviation is less than 3V, and the peak conversion efficiency is 96.2% in the case of a full load.

View full abstract

Data exchange, in which two blocks of data are swapped between cores in distributed memory systems, necessitates additional memory buffer in a multiprocessor system-on-chip. In this paper, we propose a novel bidirectional inter-core communication mechanism called coherent direct memory access (CoDMA). The CoDMA ensures that the writing address is always less than the reading address in coherent read and write mode, so as to avoid read-after-write (RAW) errors. It features an efficient data exchanging scheme without using data buffer in the memory. A four-core single-instruction multiple-data processor is established for the experiments, based on a multi-bus network-on-chip. Experimental results show that the proposed method consumes no additional memory buffer and achieves 39% and 20% average performance improvement compared with traditional Methods 1 and 2, respectively. And a maximal of 43% reduction in memory usage is achieved, at the cost of only 0.22% more area overhead compared with the entire system.

View full abstract