IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
Volume E95.C, Issue 12
Displaying 1-7 of 7 articles from this issue
Regular Section
  • Kazuyoshi SAKAMOTO, Yasushi ITOH
    Article type: PAPER
    Subject area: Microwaves, Millimeter-Waves
    2012 Volume E95.C Issue 12 Pages 1839-1845
    Published: December 01, 2012
    Released on J-STAGE: December 01, 2012
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    L-band SiGe HBT frequency-tunable differential amplifiers with dual-bandpass or dual-bandstop responses have been developed for the next generation adaptive and/or reconfigurable wireless radios. Varactor-loaded dual-band resonators comprised of series and parallel LC circuits are employed in the output circuit of differential amplifiers for realizing dual-bandpass responses as well as the series feedback circuit for dual-bandstop responses. The varactor-loaded series and parallel LC resonator can provide a wider frequency separation between dual-band frequencies than the stacked LC resonator. With the use of the varactor-loaded dual-band resonator in the design of the low-noise SiGe HBT differential amplifier with dual-bandpass responses, the lower-band frequency can be varied from 0.58 to 0.77GHz with a fixed upper-band frequency of 1.54GHz. Meanwhile, the upper-band frequency can be varied from 1.1 to 1.5GHz for a fixed lower-band frequency of 0.57GHz. The dual-band gain was 6.4 to 13.3dB over the whole frequency band. In addition, with the use of the varactor-loaded dual-band resonator in the design of the low-noise differential amplifier with dual-bandstop responses, the lower bandstop frequency can be varied from 0.38 to 0.68GHz with an upper bandstop frequency from 1.05 to 1.12GHz. Meanwhile, the upper bandstop frequency can be varied from 0.69 to 1.02GHz for a lower bandstop frequency of 0.38GHz. The maximal dual-band rejection of gain was 14.4dB. The varactor-loaded dual-band resonator presented in this paper is expected to greatly contribute to realizing the next generation adaptive and/or reconfigurable wireless transceivers.
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  • Seyed Amir HASHEMI, Hassan GHAFOORIFARD, Abdolali ABDIPOUR
    Article type: PAPER
    Subject area: Electronic Circuits
    2012 Volume E95.C Issue 12 Pages 1846-1856
    Published: December 01, 2012
    Released on J-STAGE: December 01, 2012
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    In this paper, using the Linear Time Variant (LTV) phase noise model and considering higher order harmonics generated by the oscillator output signal, a more general formula for transformation of the excess phase to the output signal is presented. Despite the basic LTV model which assumes that the total carrier power is within the fundamental harmonic, in the proposed model, the total carrier power is assumed to be distributed among all output harmonics. For the first harmonic, the developed expressions reduce to the basic LTV formulas. Simulation and experimental results are used to ensure the validity of the model.
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  • Kazutoshi KODAMA, Tetsuya IIZUKA, Toru NAKURA, Kunihiro ASADA
    Article type: PAPER
    Subject area: Electronic Circuits
    2012 Volume E95.C Issue 12 Pages 1857-1863
    Published: December 01, 2012
    Released on J-STAGE: December 01, 2012
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    This paper proposes a high frequency resolution Digitally-Controlled Oscillator (DCO) using a single-period control bit switching scheme. The proposed scheme controls the tuning word of DCO in a single period for the fine frequency tuning. The LC type DCO is implemented to realize the proposed scheme, and is fabricated using a standard 65nm CMOS technology. The measurement results show that the implemented DCO improves the frequency resolution from 560kHz to 180kHz without phase noise degradation with an additional area of 200µm2.
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  • Hung Viet NGUYEN, Myunghwan RYU, Youngmin KIM
    Article type: PAPER
    Subject area: Integrated Electronics
    2012 Volume E95.C Issue 12 Pages 1864-1871
    Published: December 01, 2012
    Released on J-STAGE: December 01, 2012
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    This paper evaluates the impact of Through-Silicon Via (TSV) on the performance and power consumption of 3D circuitry. The physical and electrical model of TSV which considers the coupling effects with adjacent TSVs is exploited in our investigation. Simulation results show that the overall performance of 3D IC infused with TSV can be improved noticeably. The frequency of the ring oscillator in 4-tier stacking layout soars up to two times compared with one in 2D planar. Furthermore, TSV process variations are examined by Monte Carlo simulations to figure out the geometrical factor having more impact in manufacturing. An in-depth research on repeater associated with TSV offers a metric to compute the optimization of 3D systems integration in terms of performance and energy dissipation. By such optimization metric with 45nm MOSFET used in our circuit layout, it is found that the optimal number of tiers in both performance and power consumption approaches 4 since the substantial TSV-TSV coupling effect in the worst case of interference is expected in 3D IC.
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  • Yoshitaka HIRAMATSU, Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAM ...
    Article type: PAPER
    Subject area: Integrated Electronics
    2012 Volume E95.C Issue 12 Pages 1872-1882
    Published: December 01, 2012
    Released on J-STAGE: December 01, 2012
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    The large data-transfer time among different cores is a big problem in heterogeneous multi-core processors. This paper presents a method to accelerate the data transfers exploiting data-transfer-units together with complex memory allocation. We used block matching, which is very common in image processing, to evaluate our technique. The proposed method reduces the data-transfer time by more than 42% compared to the earlier works that use CPU-based data transfers. Moreover, the total processing time is only 15ms for a VGA image with 16×16 pixel blocks.
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  • Peng YUE, Qian-nan LI, Xiang YI, Tuo WANG, Zeng-ji LIU, Geng CHEN, Hua ...
    Article type: BRIEF PAPER
    Subject area: Lasers, Quantum Electronics
    2012 Volume E95.C Issue 12 Pages 1883-1886
    Published: December 01, 2012
    Released on J-STAGE: December 01, 2012
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    A novel and compact electro-optic modulator implemented by a combination of a 1×2 multimode interference (MMI) coupler and an integrated Mach-Zehnder interferometer (MZI) modulator consisting of a microring and a phase modulator (PM) is presented and analyzed theoretically. It is shown that the proposed modulator offers both ultra-linearity and high output RF gain simultaneously, with no requirements for complicated and precise direct current (DC) control.
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  • Fitzgerald Sungkyung PARK, Nikolaus KLEMMER
    Article type: BRIEF PAPER
    Subject area: Integrated Electronics
    2012 Volume E95.C Issue 12 Pages 1887-1890
    Published: December 01, 2012
    Released on J-STAGE: December 01, 2012
    JOURNAL RESTRICTED ACCESS
    A fractional-N phase-locked loop (PLL) is designed for the DigRF interface. The digital part of the PLL mainly consists of a dual-mode phase frequency detector (PFD), a digital counter, and a digital delta-sigma modulator (DSM). The PFD can operate on either 52MHz or 26MHz reference frequencies, depending on its use of only the rising edge or both the rising and the falling edges of the reference clock. The interface between the counter and the DSM is designed to give enough timing margin in terms of the signal round-trip delay. The circuitry is implemented using a 90-nm CMOS process technology with a 1.2-V supply, draining 1mA.
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