This paper presents a tutorial overview of Continuous-Time Delta-Sigma Modulators (CTDSM); their operating principles to understand what is important intuitively and architectures to achieve higher conversion efficiency and to operate low supply voltage, design methods against loop stability problem, tuning methods of the bandwidth and so on. A survey of cutting-edge CMOS implementations is described.

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The Direct Sampling Mixer (DSM) with a complex coefficient transfer function is demonstrated. The operation theory and the detail design methodology are discussed for the high order complex DSM, which can achieve large image rejection ratio by introducing the attenuation pole at the image frequency band. The proposed architecture was fabricated in a 65nm CMOS process. The measured results agree well with the theoretical calculation, which proves the validity of the proposed architecture and the design methodology. By using the proposed design method, it will be possible for circuit designers to design the DSM with large image rejection ratio without repeated lengthy simulations.

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This paper presents an ADPLL using a hierarchical TDC composed of a 4f_LO DCO followed by a divide-by-4 circuit and three stages of known phase interpolators. We derived simple design requirements for ensuring precision of the phase interpolator. The proposed architecture provides immunity to PVT and local variations, which allows calibration-free operation, as well as sub-inverter delay resolution contributing to good in-band phase noise performance. Also the hierarchical TDC makes it possible to employ a selective activation scheme for power saving. Measured performances demonstrate the above advantages and the in-band phase noise reaches -104dBc/Hz. It is fabricated in a 65nm CMOS process and the active area is 0.18mm².

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This paper considers a simple type of Dynamic Element Matching (DEM), Clocked Averaging (CLA) method referred to as one-element-shifting (OES) and its effectiveness for the implementation of high spurious-free dynamic range (SFDR) multi-bit Delta-Sigma modulators (DSMs). Generic DEM techniques are successful at suppressing the mismatch error and increasing the SFDR of data converters. However, they will induce additional glitch energy in most cases. Some recent DEM methods achieve improvements in minimizing glitch energy but sacrificing their effects in harmonic suppression due to mismatches. OES technique discussed in this paper can suppress the effect of glitch while preserving the reduction of element mismatch effects. Hence, this approach achieves better SFDR performance over the other published DEM methods. With this OES, a 3rd order, 10MHz bandwidth continuous-time DSM is implemented in 90nm CMOS process. The measured SFDR attains 83dB for a 10MHz bandwidth. The measurement result also shows that OES improves the SFDR by higher than 10dB.

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The performance of successive approximation register (SAR) analog-to-digital converter (ADC) is well balanced between power and speed compare to the conventional flash or pipeline architecture. The nonlinearities suffer from the CDAC mismatch and comparator offset degrades SAR ADC performance in terms of DNL and INL. An on chip histogram-based digitally assisted background calibration technique is proposed to cancel and relax the aforesaid nonlinearities. The calibration is performed using the input signal, watching the digital codes in the specified vicinity of the decision boundaries, and feeding back to control the compensation capacitor periodically. The calibration does not require special calibration signal or additional analog hardware which is simple and amenable to hardware or software implementations. A 9-bit SAR ADC with split CDAC has been implemented in a 65nm CMOS technology and it achieves a peak SNDR of 50.81dB and consumes 1.34mW from a 1.2-V supply. +0.4/-0.4 LSB DNL and +0.5/-0.7 LSB INL are achieved after calibration. The ADC has input capacitance of 180fF and occupies an area of 0.1×0.13mm².

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A 315MHz power-gated ultra low power transceiver for wireless sensor network is developed in 40nm CMOS. The developed transceiver features an injection-locked frequency multiplier for carrier generation and a power-gated low noise amplifier with current second-reuse technique for receiver front-end. The injection-locked frequency multiplier implements frequency multiplication by edge-combining and thereby achieves 11µW power consumption at 315MHz. The proposed low noise amplifier achieves the lowest power consumption of 8.4µW with 7.9dB noise figure and 20.5dB gain in state-of-the-art designs.

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An amplitude-redistribution technique — which improves phase-noise performance of millimeter (mm)-wave and quasi mm-wave cross-coupled VCOs by controlling the distribution of voltage swings on the oscillator nodes — is proposed. A 28-GHz VCO, fabricated in 0.13-µm CMOS technology, uses this technique and demonstrates low phase-noise performance of -112.9-dBc/Hz at 1-MHz offset and FOM_T of -187.4-dBc/Hz, which is the highest FOM_T so far reported in regard to CMOS VCOs operating above 25GHz.

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A 4th-order programmable continuous-time filter (CTF) for hard-disk-drive (HDD) read channels was developed with 65-nm CMOS process technology. The CTF cutoff frequency and boost are programmable by switching units of the operational trans-conductance amplifier (OTA) banks and the capacitor banks. The switches are operated by lifted local-supply voltage to reduce on-resistance of the transistors. The CTF characteristics were robust against process technology variations and supply voltage and temperature ranges due to the introduction of a digitally assisted compensation scheme with analog auto-tuning circuits and digital calibration sequences. The digital calibration sequences, which fit into the operation sequence of the HDD read channel, compensate for the tuning circuits of the process technology variations, and the tuning circuits compensate for the CTF characteristics over the supply voltage and temperature ranges. As a result, the CTF had a programmability of 100-1000-MHz cutoff frequency and 0-12-dB boost.

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This paper presents a new type of electromagnetic interference (EMI) measurement system. An EMI Camera LSI (EMcam) with a 12×4 on-chip 250×50µm² loop antenna matrix in 65nm CMOS is developed. EMcam achieves both the 2D electric scanning and 60µm-level spatial precision. The down-conversion architecture increases the bandwidth of EMcam and enables the measurement of EMI spectrum up to 3.3GHz. The shared IF-block scheme is proposed to relax both the increase of power and area penalty, which are inherent issues of the matrix measurement. The power and the area are reduced by 74% and 73%, respectively. EMI measurement with the smallest 32×12µm² antenna to date is also demonstrated.

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We propose a fast and precise transient response and frequency characteristics simulation method for switching converters. This method uses a behavioral simulation tool without using a SPICE-like analog simulator. The nonlinear operation of the circuit is considered, and the nonlinear function is realized by defining the nonlinear formula based on the circuit operation and by applying feedback. To assess the accuracy and simulation time of the proposed simulation method, we designed current-mode buck and boost converters and fabricated them using a 0.18-µm high-voltage CMOS process. The comparison in the transient response and frequency characteristics among SPICE, the proposed program on a behavioral simulation tool which we named NSTVR (New Simulation Tool for Voltage Regulators) and experiments of fabricated IC chips showed good agreement, while NSTVR was more than 22 times faster in transient response and 85 times faster in frequency characteristics than SPICE in CPU time in a boost converter simulation.

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In this paper, we propose a new method for the bias-dependent parameter extraction of a MOSFET, which covers DC to over 100GHz. The DC MOSFET model provided by the chip foundry is assumed to be correct, and the core DC characteristics are designed to be asymptotically recovered at low frequencies. This is carried out by representing the corrections required at high frequencies using a bias-dependent Y matrix, assuming that a parasitic nonlinear two-port matrix (Y-wrapper) is connected in parallel with the core MOSFET. The Y-wrapper can also handle the nonreciprocity of the parasitic components, that is, the asymmetry of the Y matrix. The reliability of the Y-wrapper model is confirmed through the simulation and measurement of a one-stage common-source amplifier operating at several bias points. This paper will not discuss about non-linearity.

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Mirrored serpentine microstrip lines are proposed for a parallel high speed digital signaling to reduce the peak far-end crosstalk (FEXT) voltage. Mirrored serpentine microstrip lines consist of two serpentine microstrip lines, each one equal to a conventional normal serpentine microstrip line. However, one serpentine microstrip line of the mirrored serpentine microstrip lines is flipped in the length direction, and thus, two serpentine microstrip lines face each other. Time domain reflectometry measurements show that the peak FEXT voltage of the mirrored serpentine microstrip lines is reduced by 56.4% of that of conventional microstrip lines and 30.0% of that of conventional normal serpentine microstrip lines.

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This paper presents a possibility of Electromagnetic (EM) analysis against cryptographic modules outside their security boundaries. The mechanism behind the information leakage is explained from the view point of Electromagnetic Compatibility: electric fluctuation released from cryptographic modules can conduct to peripheral circuits based on ground bounce, resulting in radiation. We demonstrate the consequence of the mechanism through experiments where the ISO/IEC standard block cipher AES (Advanced Encryption Standard) is implemented on an FPGA board and EM radiations from power and communication cables are measured. Correlation Electromagnetic Analysis (CEMA) is conducted in order to evaluate the information leakage. The experimental results show that secret keys are revealed even though there are various disturbing factors such as voltage regulators and AC/DC converters between the target module and the measurement points. We also discuss information-suppression techniques as electrical-level countermeasures against such CEMAs.

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New concept of CMOS nonvolatile memory is presented with demonstration of cell implementations. The memory cell, which is a comparator basically, makes use of comparator offset for storage quantity and the FN stress phenomena for cell programming. We also propose the stress-packet operation which is the relevant programming method to finely control the offset of the memory cell. The memory cell is multiple-time programmable while it is implemented in a standard CMOS process. We fabricated the memory cell arrays of the latch comparator and demonstrated that it is rewritten several times. We also investigated the reliability of cell data retention by monitoring programmed offsets for several months.

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A nanowatt-power-level automatic switch that combines a multi-Vth CMOS level converter and an LED as a photodiode has been developed for a sensor application. The level converter is a single-input latch-type multi-Vth CMOS circuit featuring the use of an enhancement-mode nMOSFET and a depletion-mode common-gate nMOSFET as a pair of driver transistors. The ED-CMOS level converter cuts the DC current path; and the LED, which generates a high output voltage under illumination, suppresses the leakage current of the depletion-mode common-gate nMOSFET in the ED-CMOS level converter, resulting in nanowatt-order power dissipation. To verify the effectiveness of the ED-CMOS circuit, a prototype level converter was fabricated on a 0.6-µm CMOS process and used in an automatic switch in a wireless mouse. The switch is composed of two LEDs, a current-mirror circuit, the level converter, and a power switch MOSFET. It senses when a hand grabs or releases the mouse and automatically turns the mouse on or off, respectively. The measured power dissipation of the mouse is 3nW in the standby mode.

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The scattering from a phase change disk that is illuminated by an optical near field through a ridged-square nano-aperture was analyzed. A finite-difference time-domain (FDTD) method installed with motion equations of free electrons was used in the analysis and a three dimensional disk structure was taken into consideration. The far-field scattering patterns from the phase change disk were analyzed and the sum-signal output through a condenser lens was calculated. The crosstalk between plural marks and the readout characteristics of mark trains were investigated.

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This paper deals with an integral method analyzing the diffraction of a transverse electric (TE) wave by a perfectly conductive periodic surface. The conventional integral method fails to work for a critical angle of incidence. To overcome such a drawback, this paper applies the method of image Green's function. We newly obtain an image integral equation for the basic surface current in the TE case. The integral equation is solved numerically for a very rough sinusoidal surface. Then, it is found that a reliable solution can be obtained for any real angle of incidence including a critical angle.

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The operating speed scalability is demonstrated by using the forward body biasing method for a 1-V 0.18-µm CMOS true single-phase clocking (TSPC) dual-modulus prescaler. With the forward body bias voltage varying between 0 and 0.4V, the maximum operating speed changes by about 40-50% and the maximum input sensitivity frequency changes by about 400%. This speed scalability is achieved with less than 0.5-dB phase noise degradation. This demonstration indicates that the forward body biasing method is instrumental to build a cost-saving power-efficient 1-V 0.18-µm CMOS radio for low-power WBAN and WSN applications.

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A novel hybrid latch based flip-flop scheme is introduced in this paper. A pulse generator is eliminated to simplify clock distribution and save power. It also achieves high speed by shortening the critical data path. In addition, it avoids output node glitches which exist in conventional hybrid latch based flip-flops. HSPICE simulation results revealed that the proposed PHLFF performs best among referenced schemes. It can reduce 47.5% power dissipation, 16.5% clock-to-output latency and 56.4% PDP, as compared to conventional HLFF.

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This paper proposes a write resistance tracking circuit (WRTC) to improve the memory window of HfOx-based resistive memory. With a 50-ns single voltage pulse, the minimal resistance of the high resistance state in the 1-kb array of resistive switching elements can increase from 25kΩ to 65kΩ by using the proposed verify circuit. The WRTC uses the transition current detection method based on the feedback of the memory cell to control the write driver. The WRTC achieves distinct bistable resistance states, avoids the occurrence of over-RESET, and enhances the memory window of the RRAM cell.

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