We review our recent work on Yb-doped and hybrid-structured solid photonic bandgap fibers (Yb-HS-SPBGFs) for linearly-polarized fiber lasers oscillating in the small gain wavelength range from 1160nm to 1200nm. The stack-and-draw or pit-in-jacket method is employed to fabricate two Yb-HS-SPBGFs. Both of the fiber shows optical filtering property for eliminating ASE in the large gain wavelength range from 1030nm to 1130nm and enough high birefringence for maintaining linear polarization, thanks to the photonic bandgap effect and the induced birefringence of the hybrid structure. The fiber attenuation of the Yb-HS-SPBGF fabricated by the pit-in-jacket method is much lower than that of the Yb-HS-SPBGF fabricated by stack-and-draw method. Linearly-polarized single stage fiber lasers using Yb-HS-SPBGFs are also demonstrated. Laser oscillation at 1180nm is confirmed without parasitic lasing in the fiber lasers. High output power and high slope efficiency in linearly-polarized single-cavity fiber laser using the low-loss Yb-HS-SPGF fabricated by the pit-in-jacket method are achieved. Narrow linewidth, high polarization extinction ratio and high beam quality are also confirmed, which are required for high-efficient frequency-doubling. A compact and high-power yellow-orange frequency-doubling laser would be realized by using a linearly-polarized single-cavity fiber laser employing a low-loss Yb-HS-SPBGF.

View full abstract

A bidirectional amplification module has been proposed for use in IP-over-CWDM networks. The module is based on a bidirectional erbium-doped fiber amplifier. The loss compensation characteristics of the module obtained in a bidirectional IP transmission experiment confirmed that the losses of the optical node and the transmission fiber in the network can be compensated for effectively by the module making it possible to increase the number of nodes and the total fiber length of the network.

View full abstract

We demonstrate an all-optical picosecond pulse duration-tunable nonreturn-to-zero (NRZ)-to-return-to-zero (RZ) data format conversion using a Raman amplifier-based compressor and a fiber-based four-wave mixing (FWM) switch. A NRZ data signal is injected into the fiber-based FWM switch (AND gate) with a compressed RZ clock by the Raman amplifier-based compressor, and convert to RZ data signal by the fiber-based FWM switch. The compressed RZ clock train acts as a pump signal in the fiber-based FWM switch to perform the NRZ-to-RZ data format conversion. By changing the Raman pump power of the Raman amplifier-based compressor, it is possible to tune the pulse duration of the converted RZ data signal from 15ps to 2ps. In all the tuning range, the receiver sensitivity at bit error rate (BER) of 10^-9 for the converted RZ data signal was about 1.3∼1.7dB better than the receiver sensitivity of the input NRZ data signal. Moreover, the pulse pedestal of the converted RZ data signals is well suppressed owing to the FWM process in the fiber-based FWM switch.

View full abstract

High-performance 1.3-µm electroabsorption modulators integrated with DFB lasers are developed for long-reach 100Gbit Ethernet. The dynamic extinction ratio of over 8-dB with the voltage swing of 2V are achieved for the four LAN-WDM lanes (14nm wavelength range) used in 100Gbit Ethernet with the same modulator structure. The fabricated devices are packaged in butterfly modules and four-lane 40-km single mode fiber transmission at 25-Gbit/s operation is demonstrated. Further, a can-type transmitter optical subassembly is fabricated to reduce the cost and size of transmitter modules. The use of a low-dielectric-constant liquid crystal polymer transmission line makes the 3-dB bandwidth larger and enables 25-Gbit/s operation with CAN-TOSA module.

View full abstract

Silicon Mach-Zehnder interferometric (MZI) waveguide modulator incorporating the n-channel junction field-effect transistor (JFET) as a signal modulation unit was designed, fabricated, and analyzed. The proposed MZI with JFET was designed to operate based on the plasma dispersion effect in the infrared wavelength of 1550nm. The three different modulation lengths (ML) of 500, 1000, and 2000µm while keeping the overall MZI length constant at 1.5cm were set as a general design rule for these 10µm-wide MZIs under study. When the JFET was operated in an active mode by injecting approximately 50mA current (I_s) to achieve a π phase shift, the modulation efficiency of the device was measured to be η =π/(I_s·L) $\\simeq$ 40π/A-mm. The temporal and frequency response measurements also demonstrate that the respectively rise and fall times measured using a high-speed photoreceiver were in the neighborhood of 8.5 and 7.5µsec and the 3dB roll-off frequency (f_3dB) measured was in the excess of ∼400kHz.

View full abstract

We demonstrate high baud-rate DQPSK modulation with full-ETDM technique using a novel high-speed optical IQ modulator consisting of a ridge-type optical waveguide structure on a thin LiNbO₃ substrate. Our fabrication technique achieves a drastic extension of the modulator's bandwidth and a reduction of half-wave voltage. Demonstration of 90-Gbaud NRZ-DP-DQPSK signal generation with the modulator successfully achieved a bit rate of 360-Gb/s under full-ETDM configuration.

View full abstract

We study effects of preamplifier nonlinearity on polarization mode dispersion (PMD) equalization performance of feed-forward equalizer (FFE) electronic dispersion compensation (EDC) IC. We have shown that a nonlinear limiting amplifier can be used as a preamplifier for FFE EDC IC for a 6-dB dynamic range.

View full abstract

A novel predistortion technique using an automatic average-power bias controlled diode is proposed to compensate the complicated nonlinear characteristics of a microwave class-F power amplifier using an AlGaN/GaN HEMT. The optimum value for diode bias voltage is automatically set according to detected input average RF power level. A high-efficiency 1.9GHz class-F GaN HEMT power amplifier with the automatic average-power bias control (ABC) diode linearizer achieves an improved third order inter-modulation distortion (IMD3) of better than -45dBc at a smaller than 6dB output power back-off from a saturated output power of 27dBm, without changing drain efficiency. The adjacent channel leakage power ratio (ACPR) for 1.9GHz W-CDMA signals is below -40dBc at output power levels of smaller than 20dBm for the class-F power amplifier.

View full abstract

In this paper, a 65nm 1.2V 7-bit 1GSPS folding-interpolation A/D converter with a digitally self-calibrated vector generator is proposed. The folding rate is 2 and the interpolation rate is 8. A self-calibrated vector generation circuit with a feedback loop and a recursive digital code inspection is described. The circuit reduces the variation of the offset voltage caused by process mismatches, parasitic resistors, and parasitic capacitances. The chip has been fabricated with a 65nm 1-poly 6-metal CMOS technology. The effective chip area is 0.87mm² and the power consumption is about 110mW with a 1.2V power supply. The measured SNDR is about 39.1dB when the input frequency is 250MHz at a 1GHz sampling frequency. The measured SNDR is drastically improved in comparison with the same ADC without any calibration.

View full abstract

The design and performance of a sub-nanoampere two-stage power management circuit that uses off-chip capacitors for energy accumulation are presented. Focusing on the leakage current and the transition time of the power switch transistor, we estimated the minimum current for accumulating. On the basis of the results, we devised a two-stage power management architecture for sub-nanoampere operation. The simulated and experimental results for the power management circuit describe the accumulating operation with a 1-nA current source.

View full abstract

This paper presents a novel charge transfer CMOS readout circuit for an X-ray time delay and integration (TDI) array with a depth of 64. In this study, a charge transfer readout scheme based on CMOS technology is proposed to sum 64 stages of the TDI signal. In addition, a dead pixel elimination circuit is integrated within a chip, thus resolving the weakness of TDI arrays related to defective pixels. The proposed method is a novel CMOS solution for large depth TDI arrays. Thus, a high signal-to-noise ratio (SNR) can be acquired due to the increased TDI depth. The readout chip was fabricated with a 0.6µm standard CMOS process for a 150×64 CdTe X-ray detector array. The readout circuit was found to effectively increase the charge storage capacity up to 1.6×10⁸ electrons, providing an improved SNR by a factor of approximately 8. The measured equivalent noise charge resulting from the readout circuit was 1.68×10⁴ electrons, a negligible value compared to the shot noise from the detector.

View full abstract

This paper proposed a novel platform for sensor nodes to resolve the energy and latency challenges. It consists of a processor, an adaptive compressing module and several compression accelerators. We completed the proposed chip in a 0.18µm HJTC CMOS technology. Compared to the software-based solution, the hardware-assisted compression reduces over 98% energy and 212% latency. Besides, we balanced the energy and latency metric using an adaptive module. According to the scheduling algorithm, the module tunes the state of the compression accelerator, as well as the sampling frequency of the online sensor. For example, given a 9µs constraint for a 1-byte operation, it reduces 34% latency while the energy overheads are less than 5%.

View full abstract

Advanced nanometer circuits are susceptible to errors caused by process, voltage, and temperature (PVT) variations or due to a single event upset (SEU). State-of-the-art design-for-variability (DFV)-aware flip-flops (FFs) suffer from their area and timing overheads. By utilizing C-element modules, two types of FFs are proposed for error detection and error correction.

View full abstract

This brief paper describes a background calibration algorithm for a pipelined ADC with an open-loop amplifier using a Split ADC structure. The open-loop amplifier is employed as a residue amplifier in the first stage of the pipelined ADC to realize low power and high speed. However the residue amplifier as well as the DAC suffer from gain error and non-linearity, and hence they need calibration; conventional background calibration methods take a long time to converge. We investigated the split ADC structure for its background calibration with fast convergence, and validated its effectiveness by MATLAB simulation.

View full abstract

A planar miniaturized branch-line coupler with harmonic suppression property for UHF band applications is presented in this paper. By properly synthesizing the LC-tanks that employ artificial transmission lines, two pairs of quarter-wavelength branch-lines to respectively meet characteristic impedances of 35.4 and 50 ohms can be obtained with the coupler. For the operating band, it can achieve good 3dB power division with a 90° phase difference in the outputs of the through and coupled arms. The coupler also has a small area of 20.5(L) × 18(W)mm², corresponding to 0.11λg×0.1λg at 922MHz. Compared with conventional couplers, the proposed design not only offers a wide bandwidth of more than 230MHz within ±1° or ±1dB, but also works with additional harmonic suppression for achieving better performance. Therefore, the proposed branch-line coupler with a compact size is well suitable for power division application.

View full abstract

An analog controlled Variable Gain LNA (VGLNA) with tunable operating frequency bands is reported. The analog control circuit for the continuous gain variation is proposed as a low voltage version. The fabricated LNA based on 0.18µm CMOS shows a gain range of 15 ∼ -12dB (27dB gain control), a noise figure (NF) of 2dB, and an IIP3 of -10dBm while 5mA is drawn from a 1.2V supply over the frequency range of 470∼880MHz.

View full abstract