A low frequency electric field probe that integrates data acquisition and storage is developed in this paper. An electric small monopole antenna printed on the circuit board is used as the receiving antenna; the rear end of the monopole antenna is connected to the integral circuit to achieve the flat frequency response; the logarithmic detection method is applied to obtain a high measurement dynamic range. In addition, a Microprogrammed Control Unit is set inside to realize data acquisition and storage. The size of the probe developed is not exceeding 20 mm × 20 mm × 30 mm. The field strength 0.2 V/m ~ 261 V/m can be measured in the frequency range of 500 Hz ~ 10 MHz, achieving a dynamic range over 62 dB. It is suitable for low frequency electric field strength measurement and shielding effectiveness test of small shield.

Silica-LiNbO₃ (LN) hybrid modulators have a hybrid configuration of versatile passive silica-based planar lightwave circuits (PLCs) and simple LN phase modulators arrays. By combining the advantages the two components, these hybrid modulators offer large-scale, highly-functionality modulators with low losses for advanced modulation formats. However, the reliability evaluation necessary to implement them in real transmissions has not been reported yet. In terms of reliability characteristics, there are issues originating from the difference in thermal expansion coefficients between silica PLC and LN. To resolve these issues, we propose design guidelines for hybrid modulators to mitigate the degradation induced by the thermal expansion difference. We fabricated several tens of silica-LN dual polarization quadrature phase shift keying (DP-QPSK) modulators based on the design guidelines and evaluated their reliability. The experiment results show that the modules have no degradation after a reliability test based on GR-468, which confirms the validity of the design guidelines for highly reliable silica-LN hybrid modulators. We can apply the guidelines for hybrid modules that realize heterogeneous device integration using materials with different coefficients of thermal expansion.

The accurate calculation of the inductance is the most basic problem of the inductor design. In this paper, the core flux density distribution and leakage flux in core window and winding of core-type inductor are analyzed by finite element analysis (FEA) firstly. Based on it, an improved magnetic equivalent circuit with high accuracy flux density distribution (iMEC) is proposed for a single-phase core-type inductor. Depend on the geometric structure, two leakage paths of the core window are modeled. Furthermore, the iMEC divides the magnetomotive force of the winding into the corresponding core branch. It makes the core flux density distribution consistent with the FEA distribution to improve the accuracy of the inductance. In the iMEC, flux density of the core leg has an error less than 5.6% compared to FEA simulation at 150A. The maximum relative error of the inductance is less than 8.5% and the average relative error is less than 6% compared to the physical prototype test data. At the same time, due to the high computational efficiency of iMEC, it is very suitable for the population-based optimization design.

Reference current used in sense amplifiers is a crucial factor in a single-end read manner for emerging memories. Dummy cell average read scheme uses multiple pairs of dummy cells inside the array to generate an accurate reference current for data sensing. The previous research adopts current mirror sense amplifier (CMSA) which is compatible with the dummy cell average read scheme. However, clamped bit-line sense amplifier (CBLSA) has higher sensing speed and lower power consumption compared with CMSA. Therefore, applying CBLSA to dummy cell average read scheme is expected to enhance the performance. This paper reveals that direct combination of CBLSA and dummy cell average read scheme leads to sense margin degradation. In order to solve this problem, a new array design is proposed to make CBLSA compatible with dummy cell average read scheme. Current mirror structure is employed to prevent CBLSA from being short-circuited directly. The simulation result shows that the minimum sensible tunnel magnetoresistance ratio (TMRR) can be extended from 14.3% down to 1%. The access speed of the proposed sensing scheme is less than 2 ns when TMRR is 70% or larger, which is about twice higher than the previous research. And this circuit design just consumes half of the energy in one read cycle compared with the previous research. In the proposed array architecture, all the dummy cells can be always short-circuited in totally isolated area by low-resistance metal wiring instead of using controlling transistors. This structure is able to contribute to increasing the dummy cell averaging effect. Besides, the array-level simulation validates that the array design is accessible to every data cell. This design is generally applicable to any kinds of resistance-variable emerging memories including STT-MRAM.