In the beam-type microwave power transmission system, it is required to minimize the interference with communication and the influence on the human body. Retrodirective system that re-radiates a beam in the direction of arrival of a signal is well known as a beam control technique for accurate microwave power transmission. In this paper, we newly propose to apply the retrodirective system to both transmitting and receiving antennas. The leakage to the outside of the system is expected to minimize self-convergently while following the atmospheric fluctuation and the antenna movement by repeating the retrodirective between the transmitting and receiving antenna in this system. We considered this phenomenon theoretically using an infinite array antenna model. Finally, it has been shown by the equivalent circuit simulation that stable transmission can be realized by oscillating the system.

A retrodirective system utilizing harmonic reradiation from a rectenna is developed and verified for long-range wireless power transfer applications, such as low-power or battery-less devices and lightweight aerial vehicles. The second harmonic generated by the rectifying circuit is used instead of a pilot signal, and thus an oscillator for creating the pilot signal is not required. The proposed retrodirective system consists of a 2.45 GHz transmitter with a two-element phased array antenna, a 4.9 GHz direction-of-arrival (DoA) estimation system, a phase control system, and a rectenna. The rectenna, consisting of a half-wave dipole antenna, receives microwave power from the 2.45 GHz transmitter and reradiates the harmonic toward the 4.9 GHz DoA estimation system. The rectenna characteristics and experimental demonstrations of the proposed retrodirective system are described. From measurement results, the dc output power pattern for the developed retrodirective system is in good agreement with that obtained using manual beam steering. The measured DoA estimation errors are within the range of -2.4° to 4.8°.

This paper presents two ultra-low voltage and high performance VCO ICs with novel harmonic tuned LC tank which provides different harmonic impedance and shapes the pseudo-square drain voltage waveform of transistors. In the novel tank, two additional inductors are connected between the drains of the cross-coupled pMOSFETs and the conventional LC tank, and they effectively decrease second harmonic load impedance and increase third harmonic load impedance of the transistors. In this paper, the novel harmonic tuned LC tank is applied to two different structure VCOs. These two VCOs exhibit over 2 dB better phase noise performance than conventional LC tank VCOs among all tuning range. The conventional and proposed VCO ICs are designed, fabricated and measured on wafer in 45-nm SOI CMOS technology. With novel harmonic tuned LC tank, the novel two VCOs exhibit measured best phase-noise of -125.7 and -129.3 dBc/Hz at 10 MHz offset and related FoM of -190.2 and -190.5 dBc/Hz at a supply voltage of 0.3 V and 0.35 V, respectively. Frequency tuning range of the two VCOs are from 13.01 to 14.34 GHz and from 15.02 to 16.03GHz, respectively.

A methodology for obtaining semi-custom high-power amplifiers (HPAs) is described. The semi-custom concept pertains to the notion that a selectable output power is attainable by replacing only transistors. To compensate for the mismatch loss, a new output matching network that can be easily tuned by wiring is proposed. Design equations were derived to determine the circuit parameters and specify the bandwidth limitations. To verify this methodology, a semi-custom HPA with GaN HEMTs was fabricated in the S-band. A selectable output power from 240 to 150 W was successfully achieved while maintaining a PAE of over 50% in a 19% relative bandwidth.

Extremely compact harmonic tuning circuits for class-F amplifiers are realized using composite right-/left-handed (CRLH) transmission line stubs. The proposed circuits take up only a small fraction of the amplifier circuit area and yet are capable of treating four harmonics up to the 5th with a single stub or double stub configuration. This has become possible by using the negative order resonance modes of the CRLH TL, allowing for flexible and simultaneous control of many harmonics by engineering the dispersion relation of the stub line. The CRLH harmonic tuning stubs for 2-GHz amplifiers were realized using surface mounting chip capacitors, whereas the stub for 4-GHz amplifiers was fabricated based fully on microstrip-line technology. The fabricated 2-GHz and 4-GHz GaN HEMT class-F amplifiers exhibited peak drain efficiency and peak PAE of more than 83% and 74%, respectively.

This paper presents high efficiency Class-E and compact Doherty power amplifiers (PAs) with novel harmonics termination for handset applications using a GaAs/InGaP heterojunction bipolar transistor (HBT) process. The novel harmonics termination circuit effectively reduces the insertion loss of the matching circuit, allowing a device with a compact size. The Doherty PA uses a lumped-element transformer which consists of metal-insulator-metal (MIM) capacitors on an IC substrate, a bonding-wire inductor and short micro-strip lines on a printed circuit board (PCB). The fabricated Class-E PA exhibits a power added efficiency (PAE) as high as 69.0% at 1.95GHz and as high as 67.6% at 2.535GHz. The fabricated Doherty PA exhibits an average output power of 25.5dBm and a PAE as high as 50.1% under a 10-MHz band width quadrature phase shift keying (QPSK) 6.16-dB peak-to-average-power-ratio (PAPR) LTE signal at 1.95GHz. The fabricated chip size is smaller than 1mm². The input and output Doherty transformer areas are 0.5mm by 1.0mm and 0.7mm by 0.7mm, respectively.

Envelope tracking (ET) technology provides the potential for achieving high efficiency in power amplifiers (PAs) with high peak-to-average ratio (PAR) signals. Envelope amplifiers with high fidelity, high efficiency, and wide bandwidth are critical components for the widespread application of envelope tracking. This paper presents the design of a linear-assisted switching buck converter for use in an envelope amplifier. To effectively leverage the high efficiency of buck converters and the wide bandwidth capabilities of linear amplifiers, a parallel combination of these two devices is employed in this work. A novel current-sense constant-on-time (COT) controller is proposed to coordinate this hybrid power supply. The combination mainly enables the switching converter to provide the average power required by the PA with high efficiency, while the wideband linear amplifier provides a wide range of dynamic voltages. The technique improves the efficiency of the envelope amplifier, especially for applications requiring high PAR with wider bandwidth signals. Measurement of the envelope amplifier showed an efficiency of approximately 77% with 10 W output power using LTE downlink signals. The overall ET system was demonstrated by using a GaN PA. The measured average power-added efficiency of the amplifier reached above 45% for an LTE modulated signal with 20 MHz bandwidth and PAR of 8.0 dB, at an average output power of 5 W and gain of 10.1 dB. The measured normalized RMS error is below 2.1% with adjacent channel leakage ratio of -48 dBc at an offset frequency of 20 MHz.

Satellite broadcasting of 4K/8K ultra-high definition television (UHDTV) was launched in Japan in December 2018. Because this system uses the amplitude and phase shift keying (APSK) modulation scheme, there is a need to improve the non-linear characteristics of the satellite transponders. To meet this requirement, we have been developing a 120-W-class Ku-band solid state power amplifier (SSPA) as a replacement for the currently used traveling wave tube amplifier (TWTA). In this study, we developed a gallium-nitride (GaN) SSPA and linearizer (LNZ). The SSPA achieved an output power of 120W while maintaining a power added efficiency (PAE) of 31%. We evaluated the transmission performance of 16APSK in this SSPA channel in comparison with that in the TWTA channel.

In this paper, we proposed low power consumption ASK transmitter based on the direct modulated oscillator at 60GHz-band. To achieve the proposed transmitter, high power-efficient oscillator and loss less modulator are designed. Moreover combined on-chip resonator and antenna to remove the buffer amplifier of the transmitter to reduce the power consumption and size. The proposed transmitter has been fabricated in standard 65nm CMOS process. The core area is 1130µm×590µm with pads. The operation frequency is 60.4GHz. The BER of 10^-6 is achieved under 50Mbps with power consumption of less than 260µW including the buffer amplifier. Using the proposed combined on-chip resonator and antenna, which need no buffer amplifier for transmitter and the power consumption is reduced to 180µW.

In order to achieve an antenna with robustness to metal for closed space wireless communications, two types of the folded monopole antenna with different input impedance have been studied. In this study, we propose the folded monopole antenna, which can switch the input impedance by a simple method. Both simulated and measured results show that the proposed antenna can improve robustness to the proximity of the metal.

A monocone antenna is a type of monopole antenna with wideband characteristics. In this paper, a low-profile and small monocone antenna is proposed, by loading a circular plate and three oblique short elements. The characteristics of the proposed antenna are analyzed via simulation. Consequently, a low-profile and small monocone antenna can be obtained while maintaining the wideband characteristics. The relative bandwidth of the proposed antenna (voltage standing wave ratio (VSWR) ≤ 2) is greater than 158.9%. The frequency band of digital terrestrial television broadcasting and the mobile communication systems (from 470 to 3600MHz) in Japan can be completely covered with VSWR ≤ 2. In addition, the radiation patterns of the proposed antenna are omni-directional. The proposed antenna is prototyped, and the validity of the simulation is verified through measurement.

This paper describes the theoretical analysis and experimental verification of a new type high-isolation surface-acoustic-wave (SAW) duplexer by using a SAW on-chip compensation circuit designed to cancel the signal of the main SAW filter at an attenuation frequency band. First, a numerical analysis based on the interference of waves propagating parallel waveguides is applied to clarify the relation between the absolute improvement value of the filter's attenuation level and cancel conditions. Then, the feasibility of the SAW compensation circuit using the double mode SAW (DMS) resonator filter are studied in both a circuit simulation and experiment. As a result, a 10-30 dB attenuation improvement was achieved within a band range of several tens of MHz using electrical characteristics of the lower side slope in the DMS resonator filter, and that it agrees well with the result obtained by numerical analysis. These results are expected to be useful for current and future mobile systems wants higher receiver sensitivity.

High Efficiency Video Coding (HEVC) standard is now becoming one of the most widespread video coding standards in the world. As a successor of H.264 standard, it aims to provide a much superior encoding performance. To fulfill this goal, several new notations along with the corresponding computation processes are introduced by this standard. Among those computation processes, the integer motion estimation (IME) is one of bottlenecks due to the complex partitions of the inter prediction units (PU) and the large search window commonly adopted. Many algorithms have been proposed to address this issue and usually put emphasis on a large search window and great computation amount. However, the coding efforts should be related to the scenes. To be more specific, for relatively static videos, a small search window along with a simple search scheme should be adopted to reduce the time cost and power consumption. In view of this, a micro-code-based IME engine is proposed in this paper, which could be applied with search schemes of different complexity. To test the performance, three different search schemes based on this engine are designed and evaluated under HEVC test model (HM) 16.9, achieving a B-D rate increase of 0.55/-0.07/-0.14%. Compared with our previous work, the hardware implementation is optimized to reduce 64.2% of the SRAMs bits and 32.8% of the logic gate count. The final design could support 4K×2K @139/85/37fps videos @500MHz.

In this paper, a new transceiver system for the in-vehicle communication system is proposed to enhance data transmission rate and timing accuracy in TDM-based application. The proposed system utilizes point-to-point (P2P) channel, a closed-loop clock forwarding path, and a transceiver with a repeater and clock delay adjuster. The proposed system with 4 ECU (Electronic Computing Unit) nodes is implemented in 180nm CMOS technology and, when compared with conventional bus-based system, achieved more than 125 times faster data transmission. The maximum data rate was 2.5Gbps at 1.8V power supply and the worst peak-to-peak jitter for the data and clock signals over 5000 data symbols were about 49.6ps and 9.8ps respectively.