In this paper, negative bias temperature instability (NBTI) reliability of pFETs is analyzed under the post-fabrication SRAM self-improvement scheme that we have developed recently, where cell stability is self-improved by simply applying high stress voltage to supply voltage terminal (V_DD) of SRAM cells. It is newly found that there is no significant difference in both threshold voltage and drain current degradation by NBTI stress between fresh PFETs and PFETs after self-improvement scheme application, indicating that the self-improvement scheme has no critical reliability problem.

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The effects of fluorine implantation on flicker noise and reliability of NMOSFET and PMOSFETs were concurrently investigated. The flicker noise of an NMOSFET was decreased about 66% by fluorine implantation, and that of a PMOSET was decreased about 76%. As indicated by the results, fluorine implantation is one of the methods that can be used to improve the noise characteristics of MOSFET devices. However, hot-carrier degradation was enhanced by fluorine implantation in NMOSFETs, which can be related to the difference of molecular binding within the gate oxide. On the contrary, in case of PMOSFETs, NBTI life time was increased by fluorine implantation. Therefore, concurrent investigation of hot-carrier and NBTI reliability and flicker noise is necessary in developing MOSFETs for analog/digital mixed signal applications.

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Distribution of current onset voltage (COV) as well as threshold voltage (V_TH) and drain induced barrier lowering (DIBL) in MOSFETs fabricated by 65nm technology is statistically analyzed. Although V_TH distribution follows the normal distribution, COV and DIBL deviate from the normal distribution. It is newly found that COV follows the Gumbel distribution, which is known as one of the extreme value distributions. This result of statistical COV analysis supports our model that COV is mainly determined by the deepest potential valley between source and drain.

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In order to implement complementary logic function with L-shaped tunneling field-effect transistors (TFETs), current drivability and subthreshold swing (SS) need to be improved more. For this purpose, high-k material such as hafnium dioxide (HfO₂) has been used as gate dielectric rather than silicon dioxide (SiO₂). The effects of device parameters on performance have been investigated and the design of L-shaped TFETs has been optimized. Finally, the performance of L-shaped TFET inverters have been compared with that of conventional TFET ones.

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A novel tunneling field-effect transistor (TFET) featuring the sigma-shape embedded SiGe sources and recessed channel is proposed. The gate facing the source effectively focuses the E-field at the tip of the source and eliminates the gradual turn-on issue of planar TFETs. The fabrication scheme modified from the state-of-the-art 45nm/32nm CMOS technology flows provides a unique benefit in the co-integrability and the control of I_D-V_GS characteristics. The feasibility is verified with TCAD process simulation of the device with 14nm of the gate dimension. The device simulation shows 5-order change in the drain current with a gate bias change less than 300mV.

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A gate-all-around tunneling field-effect transistor (GAA TFET) with local high-k gate-dielectric and tunneling-boost n-layer based on silicon is demonstrated by two dimensional (2D) device simulation. Application of local high-k gate-dielectric and n-layer leads to reduce the tunneling barrier width between source and intrinsic channel regions. Thus, it can boost the on-current (I_on) characteristics of TFETs. For optimal design of the proposed device, a tendency of device characteristics has been analyzed in terms of the high-k dielectric length (L_high-k) for the fixed n-layer length (L_n-layer). The simulation results have been analyzed in terms of on- and off- current (I_on and I_off), subthreshold swing (SS), and RF performances.

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In this paper, we present the validity and potential capacity of a modeling and simulation environment for the nonresonant plasmonic terahertz (THz) detector based on the silicon (Si) field-effect transistor (FET) with a technology computer-aided design (TCAD) platform. The nonresonant and “overdamped” plasma-wave behaviors have been modeled by introducing a quasi-plasma electron charge box as a two-dimensional electron gas (2DEG) in the channel region only around the source side of Si FETs. Based on the coupled nonresonant plasma-wave physics and continuity equation on the TCAD platform, the alternate-current (AC) signal as an incoming THz wave radiation successfully induced a direct-current (DC) drain-to-source output voltage as a detection signal in a sub-THz frequency regime under the asymmetric boundary conditions with a external capacitance between the gate and drain. The average propagation length and density of a quasi-plasma have been confirmed as around 100nm and 1×10¹⁹/cm³, respectively, through the transient simulation of Si FETs with the modulated 2DEG at 0.7THz. We investigated the incoming radiation frequency dependencies on the characteristics of the plasmonic THz detector operating in sub-THz nonresonant regime by using the quasi-plasma modeling on TCAD platform. The simulated dependences of the photoresponse with quasi-plasma 2DEG modeling on the structural parameters such as gate length and dielectric thickness confirmed the operation principle of the nonresonant plasmonic THz detector in the Si FET structure. The proposed methodologies provide the physical design platform for developing novel plasmonic THz detectors operating in the nonresonant detection mode.

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In this paper, a high performance current latch sense amplifier (CLSA) with vertical MOSFET is proposed, and its performances are investigated. The proposed CLSA with the vertical MOSFET realizes a 11% faster sensing time with about 3% smaller current consumption relative to the conventional CLSA with the planar MOSFET. Moreover, the proposed CLSA with the vertical MOSFET achieves an 1.11dB increased voltage gain G(f) relative to the conventional CLSA with the planar MOSFET. Furthermore, the proposed CLSA realizes up to about 1.7% larger yield than the conventional CLSA, and its circuit area is 42% smaller than the conventional CLSA.

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In this paper, we suggest a novel pnp BJT structure to improve the matching characteristics of the bipolar junction transistor (BJT) which is fabricated using standard CMOS process. In the case of electrical characteristics, the collector current density Jc of the proposed structure (T2) is a little greater than the conventional structure (T1), which contributes to the greater current gain β of the proposed structure than the conventional structure. Although the matching characteristics of the collector current density of the proposed structure is almost similar to the conventional structure, that of the current gain of the proposed structure is better than the conventional structure about 14.81% due to the better matching characteristics of the base current density of the proposed structure about 59.34%. Therefore, the proposed BJT structure is desirable for high performance analog/digital mixed signal application.

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To improve metal oxide semiconductor field effect transistors (MOSFET) performance, flat interface between gate insulator and silicon should be realized. In this paper, flattening process of Si surface below 1000°C utilizing Ar/4.9%H₂ annealing and its effect on ultrathin HfON gate insulator formation were investigated. The Si(100) substrates were annealed using conventional rapid thermal annealing (RTA) system in Ar or Ar/4.9%H₂ ambient for 1h. The surface roughness of Ar/4.9%H₂-annealed Si was small compared to that of Ar-annealed Si because the surface oxidation was suppressed. The obtained root mean square (RMS) roughness was 0.08nm (as-cleaned: 0.20nm) in case of Ar/4.9%H₂-annealed at 1000°C measured by tapping mode atomic force microscopy (AFM). The HfON surface was also able to be flattened by reduction of Si surface roughness. The electrical properties of HfON gate insulator were improved by the reduction of Si surface roughness. We obtained equivalent oxide thickness (EOT) of 0.79nm (as-cleaned: 1.04nm) and leakage current density of 3.5×10^-3A/cm² (as-cleaned: 6.1×10^-1A/cm²) by reducing the Si surface roughness.

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As means to control interface reactions between HfO₂ and Ge(100), chemical vapor deposition (CVD) of ultrathin Ta-rich oxide using Tri (tert-butoxy) (tert-butylimido) tantalum (Ta-TTT) on chemically-cleaned Ge(100) has been conducted prior to atomic-layer controlled CVD of HfO₂ using tetrakis (ethylmethylamino) hafnium (TEMA-Hf) and O₃. The XPS analysis of chemical bonding features of the samples after the post deposition N₂ annealing at 300°C confirms the formation of TaGe_xO_y and the suppression of the interfacial GeO₂ layer growth. The energy band structure of HfO₂/TaGe_xO_y/Ge was determined by the combination of the energy bandgaps of HfO₂ and TaGe_xO_y measured from energy loss signals of O 1s photoelectrons and from optical absorption spectra and the valence band offsets at each interface measured from valence band spectra. From the capacitance-voltage (C-V) curves of Pt-gate MIS capacitors with different HfO₂ thicknesses, the thickness reduction of TaGe_xO_y with a relative dielectric constant of 9 is a key to obtain an equivalent SiO₂ thickness (EOT) below 0.7nm.

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An SiO₂/Si-cap/Si_0.55Ge_0.45 heterostructure was fabricated on p-type Si(100) and strained silicon on insulator (SOI) substrates by low pressure chemical vapor deposition (LPCVD) and subsequent thermal oxidation in an O₂ + H₂ gas mixture. Chemical bonding features and valence band offsets in the heterostructures were evaluated by using high-resolution x-ray photoelectron spectroscopy (XPS) measurements and thinning the stack layers with a wet chemical solution.

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We investigated the effects of chemical treatments for removing native oxide layers on InAlN surfaces by X-ray photoelectron spectroscopy (XPS). The untreated surface of the air exposed InAlN layer was covered with the native oxide layer mainly composed of hydroxides. Hydrochloric acid treatment and ammonium hydroxide treatment were not efficient for removing the native oxide layer even after immersion for 15 min, while hydrofluoric acid (HF) treatment led to a removal in a short treatment time of 1min. After the HF treatment, the surface was prevented from reoxidation in air for 1 h. We also found that the 5-min buffered HF treatment had almost the same effect as the 1-min HF treatment. Finally, an attempt was made to apply the HF-based treatment to the metal-InAlN contact to confirm the XPS results.

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We investigated solid-phase growth reactions for the fabrication of β-FeSi₂ films from Fe and FeSi sources by reflection high-energy electron diffraction (RHEED). To enhance the interdiffusion of Fe and Si for the growth of β-FeSi₂, the use of FeSi instead of pure Fe as the source for the initial deposition was examined. The RHEED observation during the solid phase reaction indicated that the growth temperature was markedly decreased to 390K using the FeSi source. We discuss the reaction mechanism of the solid phase growth of β-FeSi₂ from Fe and FeSi sources in this paper.

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We have fabricated MOS capacitors with a hybrid floating gate (FG) consisting of Ni silicide nanodots (NiSi-NDs) and silicon-quantum-dots (Si-QDs) and studied electron transfer characteristics in the hybrid FG structures induced by the irradiation of 1310nm light. The flat-band voltage shift due to the charging of the hybrid FG under light irradiation was lower than that in the dark. The observed optical response can be attributed to the shift of the charge centroid in the hybrid FG caused by the photoexcitation of electrons in NiSi-NDs and their transfer to Si-QDs. The photoexcited electron transfer from the NiSi-NDs to the Si-QDs in response to pulsed gate voltages was also evaluated from the increase in transient current caused by the light irradiation. The amount of transferred charge is likely to increase in proportion to pulse gate voltage.

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In summary, we successfully fabricated the nonvolatile hybrid polymer 4F² memory-cell. It was based on bistable state, which was observed in PS layer that is containing a Ni nanocrystals capped with NiO tunneling barrier sandwiched by Al electrodes. The current conduction mechanism for polymer memory-cell was demonstrated by fitting the I-V curves. The electrons were charged and discharged on Ni nanocrystals by tunneling through the NiO tunneling barrier. In addition, the memory-cell showed a good and reproducible nonvolatile memory-cell characteristic. Its memory margin is about 1.4×10. The retention-time is more than 10⁵ seconds and the endurance cycles of program-and-erase is more than 250 cycles. Furthermore, Thefore, polymer memory-cell would be good candidates for nonvolatile 4F² cross-bar memory-cell.

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We have investigated the impact of O₂ annealing after SiO_x deposition on the switching behavior to gain a better understanding of the resistance switching mechanism, especially the role of oxygen deficiency in the SiO_x network. Although resistive random access memories (ReRAMs) with SiO_x after 300°C annealing sandwiched with Pt electrodes showed uni-polar type resistance switching characteristics, the switching behaviors were barely detectable for the samples after annealing at temperatures over 500°C. Taking into account of the average oxygen content in the SiO_x films evaluated by XPS measurements, oxygen vacancies in SiO_x play an important role in resistance switching. Also, the results of conductive AFM measurements suggest that the formation and disruption of a conducting filament path are mainly responsible for the resistance switching behavior of SiO_x.

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We have fabricated Pt/Si-rich oxide (SiO_x)/TiN stacked MIM diodes and studied an impact of the structural asymmetry on their resistive switching characteristics. XPS analyses show that a TiON interfacial layer was formed during the SiO_x deposition on TiN by RF-sputtering in an Ar + O₂ gas mixture. After the fabrication of Pt top electrodes on the SiO_x layer, and followed by an electro-forming process, distinct bi-polar type resistive switching was confirmed. For the resistive switching from high to low resistance states so called SET process, there is no need to set the current compliance. Considering higher dielectric constant of TiON than SiO_x, the interfacial TiON layer can contribute to regulate the current flow through the diode. The clockwise resistive switching, in which the reduction and oxidation (Red-Ox) reactions can occur near the TiN bottom electrode, shows lower RESET voltages and better switching endurance than the counter-clockwise switching where the Red-Ox reaction can take place near the top Pt electrode. The result implies a good repeatable nature of Red-Ox reactions at the interface between SiO_x and TiON/TiN in consideration of relatively high diffusibility of oxygen atoms through Pt.

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A modified modeling of residue effect on nano-electro-mechanical nonvolatile memory (NEMory) is presented for considering wet etching process. The effect of a residue under the cantilever is investigated for the optimization. The feasibility of the proposed model is investigated by finite element analysis simulations.

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We have fabricated highly-dense Si nano-columnar structures accompanied with Si nanocrystals on W-coated quartz, and characterized their local electrical transport in the thickness direction using atomic force microscopy (AFM) with a conductive cantilever. By applying DC negative bias to the bottomW electrode with respect to a grounded top electrode made of ∼10-nm-thick Au on the sample surface, current images reflecting highly-localized conduction were obtained in both contact and non-contact modes. This result is attributable to electron emission due to quasi-ballistic transport through Si nanocrystals via nanocolumnar structure.

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Acoustic energy harvesters that function in environments where sound pressure is extremely high (∼150dB), such as in engine rooms of aircraft, are expected to be capable of powering wireless health monitoring systems. This paper presents the power generation performance of a lead-zirconate-titanate (PZT) acoustic energy harvester with a vibrating PZT diaphragm. The diaphragm had a diameter of 2mm, consisting of Al (0.1µm)/PZT (1µm)/Pt (0.1µm)/Ti (0.1µm)/SiO₂ (1.5µm). The harvester generated a power of 5×10^-14W under a sound pressure level of 110dB at the first resonance frequency of 6.28kHz. It was found that the generated power was increased to 2.0×10^-13W using a sound-collecting Helmholtz resonator cone with a height of 60mm. The cone provided a Helmholtz resonance at 5.8kHz, and the generated power increased from 9.7×10^-15W to 7.3×10^-13W at this frequency. The cone was also effective in increasing the bandwidth of the energy harvester.

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For a development of energy harvesting system, the fact of radio waves and ambient RF (Radio Frequency) sources, including passive devices along with novel circuits, are very closely related to mobile charging devices and energy storage system. The use of schottky diode and voltage multiplier circuits to express on the ambient RF sources surrounding the system is one way that has seen a sudden rise in use for energy harvesting. Practically speaking, the RF and ambient sources can be provided by active and passive devices such as inductors, capacitors, diode, etc. In this paper, we present a schottky based voltage multiplier circuits for mobile charging device which integrate the power generation module with radio wave generation module. We also discuss that multi-stage schematic, e.g., three-stage schottky diode based voltage multiplier circuits, for a continuing effort on energy harvesting system.

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Ultra-wideband (UWB) pulse radar has high range resolution and permeability in a dielectric medium, and has great potential for the non-destructive inspection or early-stage detection of breast cancer. As an accurate and high-resolution imaging method for targets embedded in a dielectric medium, extended range points migration (RPM) has been developed. Although this method offers an accurate internal target image in a homogeneous media, it assumes the permittivity of the dielectric medium is given, which is not practical for general applications. Although there are various permittivity estimation methods, they have essential problems that are not suitable for clear, dielectric boundaries like walls, or is not applicable to an unknown and arbitrary shape of dielectric medium. To overcome the above drawbacks, we newly propose a permittivity estimation method suitable for various shapes of dielectric media with a clear boundary, where the dielectric boundary points and their normal vectors are accurately determined by the original RPM method. In addition, our method iteratively compensates for the scattered waveform deformation using a finite-difference time domain (FDTD) method to enhance the accuracy of the permittivity estimation. Results from a numerical simulation demonstrate that our method achieves accurate permittivity estimation even for a dielectric medium of wavelength size.

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Optical buffering has been one of the major technical challenges in realizing optical packet switching routers and interconnects. We demonstrate a compact optical buffer module, comprising an InP 1×8 phased-array switch and a silica-based delay line circuit. The integrated delay line circuit is fabricated on the silica-based planar-lightwave circuit (PLC) platform, and has the ladder architecture for reducing the size. In addition, variable optical couplers are integrated to achieve effective power equalization. Tunable and uniform buffering of up to 21ns is obtained with 3-ns temporal resolution.

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The trench-gate type high-voltage (HV) MOSFET is one of the variants of HV-MOSFET, typically with its utility segments lying on a larger power consumption domain, compared to planar HV-MOSFETs. In this work, the HiSIM_HV compact model, originally intended for planar LDMOSFETs, was adequately extended to accommodate trench-gate type HV-MOSFETs. The model formulation focuses on a closed-form description of the current path in the highly resistive drift region, specific to the trench-gate HV-MOSFETs. It is verified that the developed compact expression can capture the conductivity in the drift region, which varies with voltage bias and device technology such as trench width. The notable enhancement of current drivability can be accounted for by the electrostatic control exerted by the trench gate within the framework of this model.

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In this paper, several spiral inductors with various ground clearance structures and turns were investigated to achieve noise suppression up to the fourth harmonic (3.2GHz) regime of DDR3-1600. Their performances were characterized in terms of their capability to effectively suppress simultaneous switching noise (SSN) in the frequency region of interest. For a wider noise suppression bandwidth, a spiral inductor with large ground clearance, which provides a high self resonance frequency (SRF) as well as high inductances, was implemented. The proposed spiral inductor exhibited good noise suppression characteristics in the frequency domain and achieved 50% voltage fluctuation reduction in the time domain, compared to the identical 4-turn spiral without pattern ground structure.

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