Design of the 30nm FinFETs and Double Gate MOSFETs with the halo structure for suppressing the threshold voltage roll-off and improving the subthreshold swing at the same time is proposed for the first time. The performances of nano scale FinFETs and Double Gate MOSFETs with the halo structure are analyzed using a two-dimensional device simulator. The device characteristics, focusing especially on the threshold voltage and subthreshold slope, are investigated for the different gate length, body thickness, and halo impurity concentration. From the viewpoint of body potential control, it is made clear on how to design the halo structure to suppress the short channel effects and improve the subthreshold-slope. It is shown that by introducing the halo structure to FinFETs and Double Gate MOSFETs, nano-scale FinFETs and Double Gate MOSFETs achieve an improved S-factor and suppressed threshold voltage V_th roll-off simultaneously.

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We propose a gate-all-around tunnel field effect transistor (GAA TFET) having a n-doped layer at the source junction and investigate its electrical characteristics with device simulation. By introducing the n-doped layer, band-to-band tunneling area is increased and tunneling barrier width is decreased. Also, electric field induced by gate bias is increased by the surrounding gate structure, which makes it possible to obtain a more abrupt band-bending. These effects bring about a significant improvement in on-current and subthreshold characteristics. GAA TFET with n-doped layer shows subthreshold swing at I_d =1nA/µm of 32.5mV/dec, average subthreshold swing of 20.6mV/dec. With comparison to other TFET structures, the merits of the proposed device are demonstrated and performance dependences on device parameters are characterized by extensive simulations.

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We report successful bottom-up synthesis of small diameter silicon nanowires (SiNWs) on SiO₂ and Si₃N₄ surfaces. SiNWs with diameter comparable to the diameter of the Au nano-particles (10-20nm) were grown on these surfaces, as well as on Si substrates which are commonly used for the nanowire growth. The growth temperature for obtaining a high density of SiNWs on SiO₂ and Si₃N₄ substrates is higher (460-470°C) than that of the case of normal Si substrates (440°C). The growth on patterned substrates demonstrates that SiNWs can be selectively grown. Furthermore, the guided growth over metal structures is also shown to be possible. Selective growth of SiNWs on pre-patterned surfaces opens up the possibility of self-aligning SiNWs for the integration of complex device structures.

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We have studied transmission property of electron in vertical MOSFET (V-MOSFET) from the viewpoint of quantum electro-dynamics. To obtain the intuitive picture of electron transmission property through channel of the V-MOSFET, we solve the time-dependent Schrödinger equation in real space by employing the split operator method. We injected an electron wave packet into the body of the V-MOSFET from the source, and traced the time-development of electron-wave function in the body and drain region. We successfully showed that the electron wave function propagates through the resonant states of the body potential. Our suggested approaches open the quantative and intuitive discussion for the carrier dynamics in the V-MOSFET on quantum limit.

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The excellent performance of the 10nm gate Multi-Nano-Pillar type (M-) Vertical MOSFET has been numerically shown for the first time. It is made clear that the M-Vertical MOSFET, in comparison with the conventional Single Pillar type (S-) Vertical MOSFET, has achieved an increased driving current by more than 2 times, a nearly ideal S-factor, and a suppressed cutoff-leakage current by less than 1/60 by suppressing both the short channel effect and the DIBL effect. Moreover, mechanisms of these improvements of the M-Vertical MOSFET are made clear. From all of the above, it is shown that the M-Vertical MOSFET is a key device candidate for future high speed and low power LSI's in the sub-10nm generation.

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We have revealed that the electronic states in the electrodes give a significant influence to the electron transport in nano-electronic devices. We have theoretically investigated the time-evolution of electron transport from a two-dimensional electron gas (2DEG) to a quantum dot (QD), where 2DEG represents the electrode in the nano-electronic devices. We clearly showed that the coherent electron transport is remarkably modified depending on the initial electronic state in the 2DEG. The electron transport from the 2DEG to the QD is strongly enhanced, when the initial state of the electron in the 2DEG is localized below the QD. We have proposed that controlling the electronic state in the electrodes could realize a new concept device function without modifying the electrode structures; that achieves a new controllable state in future nano-electronic devices.

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Silicon-quantum-dots (Si-QDs) with an areal density as high as ∼10¹²cm^-2 were self-assembled on thermally-grown SiO₂ by low pressure CVD using Si2H6, in which OH-terminated SiO₂ surface prior to the Si CVD was exposed to GeH₄ to create nucleation sites uniformly. After thermal oxidation of Si-QDs surface, two-dimensional electronic transport through the Si-QDs array was measured with co-planar Al electrodes evaporated on the array surface. Random telegraph signals were clearly observed at constant applied bias conditions in dark condition and under light irradiation at room temperature. The result indicates the charging and discharging of a dot adjacent to the percolation current path in the dots array.

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We experimentally studied the polarization mode dispersion (PMD) tolerance of an feed-forward equalizer (FFE) electronic dispersion compensation (EDC) IC in the absence of adaptive control, in 43-Gbit/s RZ-DQPSK transmission. Using a 3-tap FFE IC composed of InP HBTs, differential group delay (DGD) tolerance at a 2-dB Q penalty is shown to be extended from 25ps to up to 29ps. When a polarization scrambler is used, the tolerance is further extended to 31ps. This value is close to the tolerance obtained with adaptive control, without a polarization scrambler.

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We investigated the influence of the thickness of the AlN interlayer for InAlN/GaN and InAlN/AlGaN/GaN heterostructures. The AlN thickness strongly affects the surface morphology and electron mobility of the InAlN/GaN structures. The rms roughness of the surface increases from 0.35 to 1.2nm with increasing AlN thickness from 0 to 1.5nm. Large pits are generated when the AlN is thicker than 1nm. The highest electron mobility of 1470cm²/V·s is obtained for a 0.75-nm-thick AlN interlayer. The mobility, however, becomes lower with increasing deviation from 0.75nm. It is only 200cm²/V·s for the 0-nm thick AlN. Inserting AlGaN between AlN and InAlN suppresses the influence of the AlN interlayer thickness. A smooth surface with rms roughness of 0.35nm is obtained for all samples with 0-1.5-nm-thick AlN. The electron mobility ranges from 1000 to 1690cm²/V·s. The variation is smaller than that for InAlN/GaN. We fabricated field effect transistors (FETs) with gate length of 2µm. The electron mobility in the access region affects the transconductance (g_m) of FETs. As a results, the influence of the AlN thickness for InAlN/GaN FETs is larger than that for InAlN/AlGaN/GaN FETs, which reduces gate leakage current. The transconductance varies from 93 to 235mS/mm for InAlN/GaN FETs. In contrast, it varies from 180 to 230mS/mm for InAlN/AlGaN/GaN FETs. These results indicate that the InAlN/AlGaN/GaN heterostructures could lead to the development of GaN-based FETs.

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We fabricated and examined current limiting effect for InP Gunn diodes with stable depletion layer mode operation of diodes for high efficiency Gunn oscillators. Current limiting at the cathode was achieved by a shallow Schottky barrier at the interface. We discussed fabrication procedure, the results for negative differential resistance and rf tests for InP Gunn diodes. It was shown that the fabricated Gunn diodes have the output power of 10.22dBm at a frequency of 90.13GHz. Its input voltage and corresponding current were 8.55V and 252mA, respectively.

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A HfO₂ as the charge-storage layer with the physical thickness thinner than 4nm in silicon-oxide-high-k oxide-oxide-silicon (SOHOS) flash memory was investigated. Compared to the conventional silicon-oxide-nitride-oxide-silicon (SONOS) flash memory, the SOHOS shows the slow operational speed and exhibits the poorer retention characteristics. These are attributed to the thin physical thickness below 4nm and the crystallization of the HfO₂ to contribute the lateral migration of the trapped charge in the trapping layer during high temperature annealing process.

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In performing the program operation of the NAND-type flash memory array, the program-inhibited cell is applied by a positive voltage at the gate, i.e., word-line (WL) on the floating channel while the program cell is applied by program voltage as the two ends, drain select line (DSL) and source select line (SSL), are turned on with grounded bit-line (BL). In this manner, the self-boosting of silicon channel to avoid unwanted program operation is made possible. As the flash memory device is aggressively scaled down and the channel doping concentration is increased accordingly, the coupling phenomena among WL, floating gate (FG)/storage node, and silicon channel, which are crucial factors in the self-boosting scheme, should be investigated more thoroughly. In this work, the dependences of self-boosting of channel potential on channel length and doping concentration in the 2-D conventional planar and 3-D FinFET NAND-type flash memory devices based on bulk-silicon are investigated by both 2-D and 3-D numerical device simulations. Since there hardly exists realistic ways of measuring the channel potential by physical probing, the series of simulation works are believed to offer practical insights in the variation of channel potential inside a flash memory device.

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In this paper, it is shown that our fabricated MTJ of 60×180nm², which is connected to the MOSFET in series by 3 levels via and 3 levels metal line, can dynamically operate with the programming current driven by 0.14µm CMOSFET. In our measurement of transient characteristic of fabricated MTJ, the pulse current, which is generated by the MOSFET with an applied pulse voltage of 1.5V to its gate, injected to the fabricated MTJ connected to the MOSFET in series. By using the current measurement technique flowing in MTJ with sampling period of 10nsec, for the first time, we succeeded in monitor that the transition speed of the resistance change of 60×180nm² MTJ is less than 30ns with its programming current of 500µA and the resistance change of 1.2kΩ.

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In this paper, we have succeeded in the fabrication of high performance Magnetic Tunnel Junction (MTJ) which is integrated in CMOS circuit with 4-Metal/1-poly Gate 0.14µm CMOS process. We have measured the DC characteristics of the MTJ that is fabricated on via metal of 3rd layer metal line. This MTJ of 60×180nm² achieves a large change in resistance of 3.52kΩ (anti-parallel) with TMR ratio of 151% at room temperature, which is large enough for sensing scheme of standard CMOS logic. Furthermore, the write current is 320µA that can be driven by a standard MOS transistor. As the results, it is shown that the DC performance of our fabricated MTJ integrated in CMOS circuits is very good for our novel spin logic (MTJ-based logic) device.

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In this work, a divide-by-2 injection locked frequency divider (ILFD) operating in the V-band with a low DC power consumption has been developed in a commercial 0.13-µm Si RFCMOS technology. The bias current path was separated from the injection signal path, which enabled a small supply voltage of 0.5V, leading to a DC power consumption of only 0.31mW. To the authors' best knowledge, this is the lowest power consumption reported for mm-wave ILFDs at the point of writing. All inductors and interconnection lines were designed based on EM (electromagnetic) simulator for precise prediction of circuit performance. With varactor tuning voltage ranged for 0-1.2V, the free-running oscillation frequency varied from 27.43 to 28.06GHz. At 0dBm input power, the frequency divider exhibited a locking range of 5.8GHz from 53 to 58.8GHz without external tuning mechanism. The fabricated circuit size is 0.72mm × 0.62mm including the RF and DC supply pads.

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A composite right/left-handed (CRLH) transmission line with demultiplexing property is proposed towards short-range functional wireless interconnects. The CRLH line is designed by analyzing dispersion relation of the microstrip line having a split-ring and a double-stub structure to realize frequency selective properties for leaky wave radiation. A prototype device is fabricated and estimated to study feasibility of the demultiplexing operation around ten GHz.

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An on-chip Charged Device Model (CDM) ESD protection method for RF ICs is proposed in a 0.13µm RF process and evaluated by using very fast Transmission Line Pulse (vf-TLP) system. Key design parameters such as triggering voltage (V_t1) and the oxide breakdown voltage from the vf-TLP measurement are used to design input ESD protection circuits for a RF test chip. The characterization and the behavior of a Low Voltage Triggered Silicon Controlled Rectifier (SCR) which used for ESD protection clamp under vf-TLP measurements are also reported. The results measured by vf-TLP system showed that the triggering voltage decreased and the second breakdown current increased in comparison with the results measured by a standard 100ns TLP system. From the HBM/CDM testing, the RF test chip successfully met the requested RF ESD withstand level, HBM 1kV, MM 100V and CDM 500V.

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We propose a character size optimization technique to reduce the number of EB shots of multi-column-cell (MCC) lithographic systems in which transistor patterns are projected with multiple column cells in parallel. Each and every column cell is capable of projecting patterns with character projection (CP) and variable shaped beam (VSB) methods. Seeking the optimal character size of characters contributes to minimizing the number of EB shots and reducing the fabrication cost for ICs. Experimental results show that the character size optimization achieved 70.6% less EB shots in the best case with an available electron beam (EB) size. Our technique also achieved 40.6% less EB shots in the best case than a conventional character sizing technique.

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We have fabricated VDP (van der Pauw) stress sensors on (111) silicon surfaces. This work focuses on a study of strain effects in VDP stress sensors, which were generally ignored in previous works, for the precise measurements of die stresses in electronic packages. The stress sensitivity was observed to be approximately 10% larger for p-type VDP sensors compared to n-type VDP sensors.

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We investigated collector current spreading in InGaAs single heterojunction bipolar transistors (SHBTs) having a collector thickness of 75nm. SHBTs were fabricated with three different emitter widths — 200, 400, and 600nm — and the highest cutoff frequency that was obtained was 468GHz. The relationship between the current density at the highest cutoff frequency and the emitter width could not be used to estimate the current spreading because it was independent of the collector-base voltage. However, the relationship between the current density with the increase in the total collector-base capacitance and the emitter width indicates current spreading in the collector. The current spreading was estimated to be approximately 90nm.

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We designed and fabricated 4H-SiC PIN avalanche photodiodes (APD) for UV detection. The thickness of an intrinsic layer in a PIN structure was optimized in order to achieve the highest quantum efficiency at the wavelength of interest. The optimized 4H-SiC PIN APDs exhibited a maximum external quantum efficiency of > 80% at the wavelength of 280nm and a gain greater than 40000. Both electrical and optical characteristics of the fabricated APDs were in agreement with those predicted from simulation.

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The programming characteristics of polysilicon-aluminum oxide-nitride-oxide-silicon (SANOS) nonvolatile memory devices with Al₂O₃ and SiO₂ stacked tunneling layers were investigated. The electron and hole drifts in the Si₃N₄ layer were calculated to determine the program speed of the proposed SANOS devices. Simulation results showed that enhancement of the programming speed in SANOS was achieved by utilizing SiO₂ and Al₂O₃ stacked tunneling layers.

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The multilevel dual-channel (MLDC) not-AND (NAND) flash memories cell structures with asymmetrically-doped channel regions between the source and the drain were proposed to enhance read and program verifying speeds. The channel structure of the MLDC flash memories consisted of two different doping channel regions. The technical computer aided design simulation results showed that the designed MLDC NAND flash cell with asymmetrically-doped channel regions provided the high-speed multilevel reading with a wider current sensing margin and the high-speed program verifying due to the sensing of the discrete current levels. The proposed unique MLDC NAND flash memory device can be used to increase read and program verifying speed.

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With the process scaling, the leakage current reduction has been the primary design concerns in a nanometer-era VLSI circuit. In this paper, we propose a new lithography process-aware edge effects correction method to reduce the leakage current in the shallow trench isolation (STI). We construct the various test structures to model I_leakage and I_{leakage_fringe} which represent the leakage currents at the center and edge of the transistor, respectively. The layout near the active edge is modified using the look-up table generated by the calibrated analytic model. On average, the proposed edge effects correction method reduces the leakage current by 18% with the negligible decrease of the drive current at sub-40nm DRAM device.

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A low-voltage quadrature up-conversion CMOS mixer for 5-GHz wireless communication applications is designed with a TSMC 0.18-µm process. The fold-switching technique is used to implement the low-voltage double balanced quadrature mixer. A miniature lumped-element microwave broadband rat-race hybrid and RLC shift network are used for the local oscillator and the intermediate frequency port design, respectively. The measured results demonstrate that the mixer can reach a high conversion gain, a low noise figure (NF), and a high linearity. The mixer exhibits improvement in noise, conversion gain, and image rejection. The mixer shows a conversion gain of 16dB, a noise figure of 12.8dB, an image rejection of 45dB, while dissipating 15.5mW for an operating voltage at 1V.

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Tin and its alloys have been applied for the plating of electrical contacts for low electrical power conditions. In particular, tin-plated contacts are widely used as connector contacts in automotive applications and as make-break contacts in keyboard switches. In the relationship between contact resistance (R) and contact load (W) for both solid and plated tin, singularities have been found. Previously established and well known theories on the deformation of contact interfaces cannot explain these singularities. In this study, to clarify these singularities, and to obtain a contact model explaining this phenomenon, contact traces for contact load were examined by SEM and STM. The obtained microscopic images indicated piling-up at the periphery of the contact area for both solid and plated tin. In this case the contact configuration comprised a platinum probe with a hemispherical tip surface and a flat tin surface for both solid and plated. When the probe was loaded, this tip of the probe sank into the soft tin surface owing to its lower hardness. In case of solid tin, the sinking of the probe surface into the tin surface causes piling-up around the periphery of the contact trace. In this deformation process, since the periphery of the indentation of the indented contact area severely slid against the surface of the platinum probe while applying a contact load, the contact resistance rapidly decreased with load. In this case, the center portion of the true contact area was not affected mechanically; thus, the surface film on the bottom portion of the deformed of the flat surface did not break down mechanically. On the other hand, in the case of a tin plated surface, similar piling up occurred; however, it was accompanied by scattering and separation of tin crystal grains from the surface. As a result of this process, a decrease in contact resistance similar to that for the solid tin occurred. Since the piling-up of the contact surface is a very important process in the application of connectors, the above-mentioned unusual characteristics were clarified in this study.

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The downscaling of CMOS technology has resulted in strong improvement in RF performance of bulk and SOI MOSFETs. In order to realize a low-noise RF circuit, a deeper understanding of the noise performance for MOSFETs is required. Thermal noise is the main noise source of the CMOS device for high frequency performance, and is dominated by the drain channel noise, induced gate noise, and their correlation noise. In this work, we measured the RF noise parameter (F_min, R_n, Γ_opt) of 45nm node MOSFETs from 5 to 15GHz and extracted noise sources and noise coefficients P, R, and C by using an extended van der Ziel's model. We found, for the first time, that correlation coefficient C decreases from positive to negative values when the gate length is reduced continuously with the gate length of sub-100nm. We confirmed that Pucel's noise figure model, using noise coefficients P, R, and C, can be considered a good approximation even for sub-50nm MOSFETs. We also discussed a scaling effect of the noise coefficients, especially the correlation noise coefficient C on the minimum noise figure.

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Architecture of a low power Ternary Content Addressable Memory (TCAM) is proposed. The TCAM is a powerful engine for search and sort processing, but it has two serious problems, large power consumption and large power line noise. To solve these problems, we have developed a charge recycling scheme for match lines and search lines. A combination of the newly introduced PMOS CAM cell together with the conventional NMOS CAM cell realizes match line charge recycling. A checkerboard arrangement of the NMOS and the PMOS cell array enables search line charge recycling. By using these technologies, the power consumption of the TCAM can be reduced to 50% of conventional designs, and as a result, the power line noise is also reduced. An experimental chip has been fabricated in 180-nm 6-metal process. The power consumption of this chip is 6.3fJ/bit/search, which is half of the conventional scheme.

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To tackle the increasing testing power during built-in self-test (BIST) operations, this paper proposes a new test pattern generator (TPG). With the proposed reconfigurable LFSR, the reconfigurable Johnson counter, the decompressor and the XOR gate network, the introduced TPG can produce the single input change (SIC) sequences with few repeated vectors. The proposed SIC sequences minimize switching activities of the circuit under test (CUT). Simulation results on ISCAS benchmarks demonstrate that the proposed method can effectively save test power, and does not impose high impact on test length and hardware for the scan based design.

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A novel resonant four-way divider/combiner based on finline is presented and studied. This divider/combiner designed in 34-36GHz is composed of new probe coupling units between finline to microstrip lines. The measured power-combining efficiency of this circuit at 34.85GHz is 83%.

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In this letter, a highly linear 1.22GHz current mirror based differential RF programmable gain amplifier (RFPGA) for digital TV tuner applications is proposed and implemented using 0.18-µm CMOS process. The fabricated RFPGA shows a maximum power gain of 9dB, an OIP3 of 23.5dBm, and an accurate dB-linear discrete gain step control while consuming 36mA from a 1.8-V supply voltage.

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A new mixed-voltage I/O buffer for low-voltage low-latency operation is proposed in this paper. The proposed buffer adopts a novel delay-based timing-control scheme to efficiently avoid problems like gate-oxide stress and hot-carrier degradation. The proposed timing-control scheme also allows the buffer to have a lower latency for transmitting data by avoiding the use of timing-critical circuits like series-connected transmission gates (TGs) and triple-stacked transistors. The latency for receiving data at low supply voltage is also reduced by employing a variable stacked transistor gate-biasing scheme. Comparison results in an 80-nm CMOS process indicated that the proposed mixed-voltage I/O buffer improved up to 79.3% for receiving the external data and up to 23.8% for transmitting the internal data at a supply voltage of 1.2V.

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A new pixel design and driving method for active matrix organic light emitting diode (AMOLED) displays that use low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) with a voltage programming method are proposed and verified using the SPICE simulator. We had employed an appropriate TFT model in SPICE simulation to demonstrate the performance of the pixel circuit. The OLED anode voltage variation error rates are below 0.35% under driving TFT threshold voltage deviation (Δ V_th =± 0.33V). The OLED current non-uniformity caused by the OLED threshold voltage degradation (Δ V_TO =+0.33V) is significantly reduced (below 6%). The simulation results show that the pixel design can improve the display image non-uniformity by compensating for the threshold voltage deviation in the driving TFT and the OLED threshold voltage degradation at the same time.

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