This paper proposes a novel high-temperature superconducting dual-band bandpass filter (HTS-DBPF), that employs a broadside coupling structure, in which quarter-wavelength resonators are formed on opposite sides of each substrate. This structure provides a dual-band operation of the BPF and flexibility, in the sense of having a wide range in selecting two center passband frequencies of the HTS-DBPF. This paper employs the ratio of the lower and higher center passband frequencies, α, as a criterion for evaluating the flexibility. The obtained α ranges are from 1 to 4.7, which are the widest for DBPFs for mobile communications applications, to the best knowledge of the authors. This paper presents a 2.4-/2.9-GHz band HTS-DBPF, as an experimental example, using a YBCO film deposited on an MgO substrate. The measured frequency responses of the HTS-DBPF agree with the electromagnetic simulated results. Measurement and simulation results confirm that the proposed filter architecture is effective in configuring a DBPF that can set each center passband frequency widely.

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A plane coupler has been developed for a two-dimensional (2D) wireless power transmission. This coupler can construct a continuous wireless power transmission system for mobile devices due to its small, light characteristics. This coupler has two elements connected with a 2D waveguide sheet, and coupling capacitances between the elements and the sheet decrease the coupler size by reducing their resonance frequencies. A propagation loss of -10.0dB is obtained using the small 0.025-λ² coupler. Continuous operation of the mobile device is demonstrated by applying wireless power transmission to the 2D waveguide sheet with the small plane coupler.

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A complete 4-level pulse amplitude modulation (4-PAM) serial link transceiver including a wide frequency range clock generator and clock data recovery (CDR) is proposed in this paper. A dual-loop architecture, consisting of a frequency locked loop (FLL) and a phase locked loop (PLL), is employed for the wide frequency range clocks. The generated clocks from the FLL (clock generator) and the PLL (CDR) are utilized for a transmitter clock and a receiver clock, respectively. Both FLL and PLL employ the identical voltage controlled oscillators consisting of ring-type delay-cells. To improve the frequency tuning range of the VCO, deep triode PMOS loads are utilized for each delay-cell, since the turn-on resistance of the deep triode PMOS varies substantially by the gate-voltage. As a result, fabricated in a 0.13-µm CMOS process, the proposed 4-PAM transceiver operates from 1.5Gb/s to 9.7Gb/s with a bit error rate of 10^-12. At the maximum data-rate, the entire power dissipation of the transceiver is 254mW, and the measured jitter of the recovered clock is 1.61ps_rms.

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We have optimized and evaluated organic thin-film solar cell devices with a structure of graded junction. The graded junction consisting of donor and accepter materials was fabricated by varying the deposition rates of both materials with a continuous grading, using two evaporation sources of cupper phthalocyanine and fullerene as p- and n-type materials, respectively. By evaluating device characteristics, optimized device structure ITO/CuPc (10nm)/graded layer (35nm)/C₆₀ (15nm)/BCP (10nm)/Ag (100nm) with an efficiency of 1.36% was obtained. In the structure, short-circuit current density was the largest and existence of larger voltage dependence in current density was observed. In addition, we have measured temperature dependences of current density versus voltage characteristics in the graded organic solar cell under illumination. The carrier extraction was enhanced by changing voltage possibly due to the internal electric field of the graded junction.

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Two voltage controlled current source (VCCS) models of double-channel p-type lateral extended drain MOS (DPLEDMOS) are firstly proposed to analyze the energy recovery circuit (ERC) efficiency of PDP data driver IC. In terms of the mathematical function between I_D and V_DS, the VCCS models are created. The presented models can be embedded in system software Saber to simulate the ERC waveform of data driver IC. A test board and a PDP system are used to verify the accuracy of the VCCS models. The experimental measurements agree with the simulation results very well and the maximum model error is 3.89%. Simulation results also show that the ERC efficiency of PDP data driver IC is influenced by three factors: the value of charge time T_ERC, the drain current I_D, and the capacitance of C_L. In an actual PDP system, T_ERC is restricted and C_L is changeless. The ERC efficiency of PDP data driver IC can be improved significantly by using DPLEDMOS which has higher I_D capacity. The proposed VCCS models of DPLEDMOS can be used to predict the ERC efficiency accurately.

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With the technology scaling down, leakage power becomes an important part of total power consumption. The relatively large leakage current weakens the energy recovery capability of adiabatic circuits and reduces its superiority, compared with static CMOS circuits in the field of low-power design. In this paper, we rebuild three types of adiabatic circuits (2N2N2P, IPAL and DCPAL) based on FinFET devices to obtain a large leakage power reduction by rationally utilizing the different operating modes of FinFET devices (SG, LP, and IG). A 16-bit adiabatic adder has been investigated to demonstrate the advantages of FinFET adiabatic circuits. The Predictive Technology Model (PTM) is used for 32-nm bulk MOSFET and FinFET devices and all of the simulations are based on HSPICE. The results evince the proposed FinFET adiabatic circuits have a considerable reduction (more than 60% for SG mode FinFET and more than 80% for LP mode FinFET) of power consumption compared with the bulk MOSFET ones. Furthermore, the FinFET adiabatic circuits also have higher limiting frequency of clock source and better noise immunity.

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Ternary content addressable memory (TCAM) is popular LSI for use in high-throughput forwarding engines on routers. However, the unique structure applied in TCAM consume huge amounts of power, therefore it restricts the ability to handle large lookup table capacity in IP routers. In this paper, we propose a commodity-memory based hardware architecture for the forwarding information base (FIB) application that solves the substantial problems of power and density. The proposed architecture is examined by a fabricated test chip with 40nm embedded DRAM (eDRAM) technology, and the effect of power reduction verified is greatly lower than conventional TCAM based and the energy metric achieve 0.01fJ/bit/search. The power consumption is almost 0.5W at 250Msps and 8M entries.

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This paper presents a fine-grain bit-serial reconfigurable VLSI architecture using multiple-valued switch blocks and binary logic modules. Multiple-valued signaling is utilized to implement a compact switch block. A binary-controlled current-steering technique is introduced, utilizing a programmable three-level differential-pair circuit to implement a high-performance low-power arbitrary two-variable binary function, and increase the noise margins in comparison with the quaternary-controlled differential-pair circuit. A current-source sharing technique between a series-gating differential-pair circuit and a current-mode D-latch is proposed to reduce the current source count and improve the speed. It is demonstrated that the power consumption and the delay of the proposed multiple-valued cell based on the binary-controlled current-steering technique and the current-source-sharing technique are reduced to 63% and 72%, respectively, in comparison with those of a previous multiple-valued cell.

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