In this study, edge diffraction of an electromagnetic plane wave by two-dimensional conducting wedges has been analyzed by the physical optics (PO) method for both E and H polarizations. Non-uniform and uniform asymptotic solutions of diffracted fields have been derived. A unified edge diffraction coefficient has also been derived with four cotangent functions from the conventional angle-dependent coefficients. Numerical calculations have been made to compare the results with those by other methods, such as the exact solution and the uniform geometrical theory of diffraction (UTD). A good agreement has been observed to confirm the validity of our method.

A linear and broadband power amplifier (PA) for 5G phased-array is presented. The design improves the linearity by operating the transistors in deep class AB region. The design broadens the bandwidth by applying the inter-stage weakly-coupled transformer. The theory of transformers is illustrated by analyzing the odd- and even-mode model. Based on this, the odd-mode Q factor is used to evaluate the quality of impedance matching. Weakly- and strongly-coupled transformers are compared and analyzed in both the design process and applicable characteristics. Besides, a well-founded method to achieve the transformer-based balanced-unbalanced transformation is proposed. The fully integrated two-stage PA is designed and implemented in a 65-nm CMOS process with a 1-V power supply to provide a maximum small-signal gain of 19dB. The maximum output 1-dB compressed power (P_1dB) of 17.4dBm and the saturated output power (P_SAT) of 18dBm are measured at 28GHz. The power-added efficiency (PAE) of the P_1dB is 26.5%. From 23 to 32GHz, the measured P_1dB is above 16dBm, covering the potential 5G bands worldwide around 28GHz.

This paper reports on X-band Gallium Nitride (GaN) chipsets for cost-effective 20W transmit-receive (T/R) modules. The chipset components include a GaN-on-Si monolithic microwave integrated circuit (MMIC) driver amplifier (DA), a GaN-on-SiC high power amplifier (HPA) with GaAs matching circuits, a high-gain GaN-on-Si HPA with a GaAs output matching circuit, and a GaN-on-Si MMIC switch (SW). By utilizing either combination of the DA or single high-gain HPA, the configurations of two T/R module types can be realized. The GaN-on-Si MMIC DA demonstrates an output power of 6.4-7.4W, an associate gain of 22.3-24.6dB and a power added efficiency (PAE) of 32-36% over 9.0-11.0GHz. A GaN-on-SiC HPA with GaAs matching circuits exhibited an output power of 20-28W, associate gain of 7.8-10.7dB, and a PAE of 40-56% over 9.0-11.0GHz. The high-gain GaN-on-Si HPA with a GaAs output matching circuit exhibits an output power of 15-30W, associate gain of 27-30dB, and PAE of 26-33% over 9.0-11.0GHz. The GaN-on-Si MMIC switch demonstrates insertion losses of 1.1-1.3dB and isolation of 10.1-14.7dB over 8.0-11.5GHz. By employing cost-effective circuit configurations, the costs of these chipsets are estimated to be about half that of conventional chipsets.

In this paper, we present a scheme to compute either AB or AB² multiplications over GF(2^m) and propose a bit-parallel systolic architecture based on the proposed algorithm. The AB multiplication algorithm is derived in the same form as the formula of AB² multiplication algorithm, and an architecture that can perform AB multiplication by adding very little extra hardware to AB² multiplier is designed. Therefore, the proposed architecture can be effectively applied to hardware constrained applications that cannot deploy AB² multiplier and AB multiplier separately.