The unique properties of superconductivity can be exploited to provide the ultimate in electronic technology for systems such as ultra-precise analogue-to-digital and digital-to-analogue converters, precise DC and AC voltage standards, ultra high speed logic circuits and systems (both digital and hybrid analogue-digital systems), and very high throughput network routers and supercomputers which would have superior electrical performance at lower overall electrical power consumption compared to systems with comparable performance which are fabricated using conventional room temperature technologies. This potential for high performance electronics with reduced power consumption would have a positive impact on slowing the increase in the demand for electrical utility power by the information technology community on the overall electrical power grid. However, before this technology can be successfully brought to the commercial market place, there must be an aggressive investment of resources and funding to develop the required infrastructure needed to yield these high performance superconductor systems, which will be reliable and available at low cost. The author proposes that it will require a concerted effort by the superconductor and cryogenic communities to bring this technology to the commercial market place or make it available for widespread use in scientific instrumentation.

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This paper presents the history of superconductor digital circuits starting from several years after the discovery of the Josephson junction in 1962. The first two decades were mainly devoted to developing voltage-state logic, which is similar to semiconductor logic. Research on circuits employing the manipulation of single magnetic flux quanta resulted in a form called RSFQ in the mid-1980s; this is the basis of superconductor logic systems of today. The more difficult problem of random access memory is reviewed. We analyze the present status of the field and outline the work that lies ahead to realize a successful superconductor digital technology.

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Superconductivity and superconducting electronics have quite a prominent place in the European research environment and can look back onto a successful history. In recent years the European Framework programs helped to enhance the interaction between the different national research institutions, universities and industry. For applications of superconductivity this was accomplished by the European Network of Excellence SCENET and its sister organization ESAS. In this context a virtual European foundry network was established (Fluxonics), which forms a platform for the superconducting electronics activities in Europe and realizes support for the design and the fabrication of superconducting circuits for research laboratories and industry. Lately quite some development on the digital side and the cooling of superconducting electronics devices has taken place in Europe; most of it within the Fluxonics network. Some of these advances will be reported in this overview article.

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We have developed the fabrication process, the circuit design technology, and the cryopackaging technology for high-T_c single flux quantum (SFQ) devices with the aim of application to an analog-to-digital (A/D) converter circuit for future wireless communication and a sampler system for high-speed measurements. Reproducibility of fabricating rampedge Josephson junctions with I_cR_n products above 1mV at 40K and small I_c spreads on a superconducting groundplane was much improved by employing smooth multilayer structures and optimizing the junction fabrication process. The separated base-electrode layout (SBL) method that suppresses the J_c spread for interface-modified junctions in circuits was developed. This method enabled low-frequency logic operations of various elementary SFQ circuits with relatively wide bias current margins and operation of a toggle-flip-flop (T-FF) above 200GHz at 40K. Operation of a 1:2 demultiplexer, one of main elements of a hybrid-type Σ-Δ A/D converter circuit, was also demonstrated. We developed a sampler system in which a sampler circuit with a potential bandwidth over 100GHz was cooled by a compact stirling cooler, and waveform observation experiments confirmed the actual system bandwidth well over 50GHz.

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Ultra fast switching speed of superconducting digital circuits enable realization of Digital Signal Processors with performance unattainable by any other technology. Based on rapid-single-flux technology (RSFQ) logic, these integrated circuits are capable of delivering high computation capacity up to 30 GOPS on a single processor and very short latency of 0.1ns. There are two main applications of such hardware for practical telecommunication systems: filters for superconducting ADCs operating with digital RF data and recursive filters at baseband. The later of these allows functions such as multiuser detection for 3G WCDMA, equalization and channel precoding for 4G OFDM MIMO, and general blind detection. The performance gain is an increase in the cell capacity, quality of service, and transmitted data rate. The current status of the development of the RSFQ baseband DSP is discussed. Major components with operating speed of 30GHz have been developed. Designs, test results, and future development of the complete systems including cryopackaging and CMOS interface are reviewed.

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Digital superconductor electronics has been experiencing rapid maturation with the emergence of smaller-scale, lower-cost communications applications which became the major technology drivers. These applications are primarily in the area of wireless communications, radar, and surveillance as well as in imaging and sensor systems. In these areas, the fundamental advantages of superconductivity translate into system benefits through novel Digital-RF architectures with direct digitization of wide band, high frequency radio frequency (RF) signals. At the same time the availability of relatively small 4K cryocoolers has lowered the foremost market barrier for cryogenically-cooled digital electronic systems. Recently, we have achieved a major breakthrough in the development, demonstration, and successful delivery of the cryocooled superconductor digital-RF receivers directly digitizing signals in a broad range from kilohertz to gigahertz. These essentially hybrid-technology systems combine a variety of superconductor and semiconductor technologies packaged with two-stage commercial cryocoolers: cryogenic Nb mixed-signal and digital circuits based on Rapid Single Flux Quantum (RSFQ) technology, room-temperature amplifiers, FPGA processing and control circuitry. The demonstrated cryocooled digital-RF systems are the world's first and fastest directly digitizing receivers operating with live satellite signals in X-band and performing signal acquisition in HF to L-band at ∼30GHz clock frequencies.

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We developed an Nb-based fabrication process for single flux quantum (SFQ) circuits in a Japanese government project that began in September 2002 and ended in March 2007. Our conventional process, called the Standard Process (SDP), was improved by overhauling all the process steps and routine process checks for all wafers. Wafer yield with the improved SDP dramatically increased from 50% to over 90%. We also developed a new fabrication process for SFQ circuits, called the Advanced Process (ADP). The specifications for ADP are nine planarized Nb layers, a minimum Josephson junction (JJ) size of 1×1μm, a line width of 0.8μm, a JJ critical current density of 10kA/cm², a 2.4Ω Mo sheet resistance, and vertically stacked superconductive contact holes. We fabricated an eight-bit SFQ shift register, a one million SQUID array and a 16-kbit RAM by using the ADP. The shift register was operated up to 120GHz and no short or open circuits were detected in the one million SQUID array. We confirmed correct memory operations by the 16-kbit RAM and a 5.7 times greater integration level compared to that possible with the SDP.

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A cryocooled system with I/O interface circuits, which enables high-speed system operation of superconductive single-flux-quantum (SFQ) circuits at over 40GHz, and the demonstration of a 47-Gbps SFQ 2×2 switch system are presented. The cryocooled system has 32 I/Os and cools an SFQ multi-chip module (MCM) to 4K with a two-stage 1W Gifford-McMahon cryocooler. An SFQ 4:1 multiplexer (MUX) and an SFQ 1:4 demultiplexer (DEMUX) have been designed to interface the speed gap between the I/O (-10Gbps/ch) and SFQ circuits (>40GHz). An SFQ 2×2 switch chip, in which the MUX/DEMUX and an SFQ 2×2 switch are integrated, and an 8-channel superconductive voltage driver (SVD) chip have been designed with an advanced cell library for a junction critical current density of 10kA/cm². An SFQ 2×2 switch MCM has been made by flip-chip bonding the switch chip and SVD chip on a superconductive MCM carrier with ∅50-μm InSn solder bumps. An SFQ 2×2 switch system, which is the switch MCM packaged in the cryocooled system, has been demonstrated up to a port speed of 47Gbps for the first time.

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We developed a 4×4 SFQ network switch prototype system and demonstrated its operation at 10Gbps. The system's core is composed of two SFQ chips: a 4×4 switch and a 6-channel voltage driver. The 4×4 switch chip contained both a switch fabric (i. e. a data path) and a switch scheduler (i. e. a controller). Both chips were attached to a multichip-module (MCM) carrier, which was then installed in a cryocooled system with 32 10-Gbps ports. Each chip contained about 2100 Josephson junctions on a 5-mm×5-mm die. An NEC standard 2.5-kA/cm² fabrication process was used for the switch chip. We increased the critical current density to 10kA/cm² for the driver chip to improve speed while maintaining wide bias margins. MCM implementation enabled us to use a hybrid critical current density technology. Voltage pulses were transferred between two chips through passive transmission lines on the MCM carrier. The cryocooled system was cooled down to about 4K using a two-stage 1-W cryocooler. We correctly operated the whole system at 10Gbps. The switch scheduler, which is driven by an on-chip clock generator, operated at 40GHz. The speed gap between SFQ and room temperature devices was filled by on-chip SFQ FIFO buffers or shift registers. We measured the bit error rate at 10Gbps and found that it was on the order of 10^-13 for the 4×4 SFQ switch fabric. In addition, using semiconductor interface circuitry, we built a four-port SFQ Ethernet switch. All the components except for a compressor were installed in a standard 19-inch rack, filling a space 21 U (933.5mm or 36.75 inches) in height. After four personal computers (PCs) were connected to the switch, we have successfully transferred video data between them.

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We describe the development of single-flux-quantum (SFQ) microprocessors and the related technologies such as designing, circuit architecture, microarchitecture, etc. Since the microprocessors studied here aim for a general-purpose computing system, we employ the complexity-reduced (CORE) architecture in which the high-speed nature of the SFQ circuits is used not for increasing processor performance but for reducing the circuit complexity. The bit-serial processing is the most suitable way to realize the CORE architecture. We assembled all the best technologies concerning SFQ integrated circuits and designed the SFQ microprocessors, CORE1α, CORE1β, and CORE1γ. The CORE1β was made up of about 11000 Josephson junctions and successfully demonstrated. The peak performance reached 1400 million operations per second with a power consumption of 3.4mW. We showed that the SFQ microprocessors had an advantage in a performance density to semiconductor's ones, which lead to the potential for constructing a high performance SFQ-circuit-based computing system.

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We propose a desk-side supercomputer with large-scale reconfigurable data-paths (LSRDPs) using superconducting rapid single-flux-quantum (RSFQ) circuits. It has several sets of computing unit which consists of a general-purpose microprocessor, an LSRDP and a memory. An LSRDP consists of a lot of, e. g., a few thousand, floating-point units (FPUs) and operand routing networks (ORNs) which connect the FPUs. We reconfigure the LSRDP to fit a computation, i. e., a group of floating-point operations, which appears in a ‘for’ loop of numerical programs by setting the route in ORNs before the execution of the loop. We propose to implement the LSRDPs by RSFQ circuits. The processors and the memories can be implemented by semiconductor technology. We expect that a 10 TFLOPS supercomputer, as well as a refrigerating engine, will be housed in a desk-side rack, using a near-future RSFQ process technology, such as 0.35μm process.

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We have designed a superconductor-semiconductor hybrid analog-to-digital (A/D) converter and experimentally evaluated its performance at sampling frequencies up to 18.6GHz. The A/D converter consists of a superconductor front-end circuit and a semiconductor back-end circuit. The front-end circuit includes a sigma-delta modulator and an interface circuit, which is for transmitting data signal to the semiconductor back-end circuit. The semiconductor back-end circuit performs decimation filtering. The design of the modulator was modified to reduce effects of integrator leak and thermal noise on signal-to-noise ratio (SNR). Using the improved modulator design, we achieved a bit-accuracy close to the ideal value. The hybrid architecture enabled us to reduce the integration scale of the front-end circuit to fewer than 500 junctions. This simplicity makes feasible a circuit based on a high T_C superconductor as well as on a low T_C superconductor. The experimental results show that the hybrid A/D converter operated perfectly and that SNR was 84.8dB (bit accuracy-13.8bit) at a band width of 9.1MHz. This converter has the highest pertormance of all sigma-delta A/D converters.

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We report on suppressing adjacent-frequency interference (AFI) by using a RF receive bandpass-filter (BPF) with high-selectivity. By considering a high temperature superconducting (HTS) multi-pole BPF as a high selective BPF, the effect was estimated by numerical simulations. The simulations of the RF signals with an OFDM modulation transmitted to the demodulator via the BPF were carried out using the HTS BPF for 5GHz band. The results confirmed the improvement of the bit error rate (BER) characteristic with the assumed HTS BPF with the high multi-poles under a strong AFI.

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The author developed a GaAs wideband IQ modulator IC, which is utilized in RF signal source instruments with direct-conversion architecture. The layout is fully symmetric to obtain a temperature-stable operation. However, thee actual temperature drift of EVM (Error Vector Magnitude) is greater in some frequency and temperature ranges than the first generation IC of the same architecture. For applications requiring the precision of electric instrumentation, temperature drift is highly critical. This paper clarifies that linear phase error is the dominant factor causing the temperature drift. It also identifies that such temperature drift of linear phase error is due to equivalent series impedance, especially parasitic capacitance of the phase shifter. This effect is verified by comparing the SSB measurements to a mathematical simulation using an empirical temperature-dependent small-signal FET model.

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This paper presents a quadrature injection locked frequency divider (ILFD) employing tunable active inductors (TAIs), which are used is to extend the locking range and to reduce die area. The CMOS ILFD is based on a new quadrature voltage-controlled oscillator (VCO) with cross-coupled switching pairs and TAI-C tanks, and was fabricated in the 0.18-μm 1P6M CMOS technology. The divide-by-2 LC-tank ILFD is performed by adding injection MOSFETs between the differential outputs of the VCO. Measurement results show that at the supply voltage of 1.8V, the divider free-running frequency is tunable from 1.34GHz to 3.07GHz, and at the incident power of 0dBm the locking range is about 6GHz (137%), from the incident frequency 1.37GHz to 7.38GHz. The core power consumption is 22.8mW. The die area is 0.63×0.55mm².

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The MOS switch with bootstrapped technique is widely used in low-voltage switched-capacitor circuit. The switched-capacitor circuit with the bootstrapped technique could be a dangerous design approach in the nano-scale CMOS process due to the gate-oxide transient overstress. The impact of gate-oxide transient overstress on MOS switch in switched-capacitor circuit is investigated in this work with the sample-and-hold amplifier (SHA) in a 130-nm CMOS process. After overstress on the MOS switch of SHA with unity-gain buffer, the circuit performances in time domain and frequency domain are measured to verify the impact of gate-oxide reliability on circuit performances. The oxide breakdown on switch device degrades the circuit performance of bootstrapped switch technique.

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Wave absorber of rubber sheet containing natural rubber and EPDM is designed, fabricated and measured for improving ETC environment. As a result, proposed absorption material has fine weatherability and wave absorption satisfied with ETC standard can be realized theoretically before and after the weatherability test if the thickness of absorber is fabricated at the ranging from 2.26mm to 2.52mm. Moreover, absorber sheet sample based on theoretical values is fabricated and are measured. As a result, 20dB or more is also confirmed at the incident angle ranging from 5 to 55 degrees experimentally. Therefore, the wave absorber with fine weatherability being satisfied with ETC standard can be realized.

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An unequal Wilkinson power divider with adjustable power dividing ratio is proposed. The proposed power divider consists of rectangular defected ground structure (DGS), isolated island in DGS, and varactor diodes. The impedance of the microstrip line greatly increases due to the DGS, and varies because of the varying capacitance of diodes. The measured unequal dividing ratios vary from 1.97-13.4 and 2.25-10.6 when 2- and 4-diodes are adopted.

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In this paper, we describe a 6-bit 1.6-GS/s flash analog to digital converter (ADC). To reduce the power consumption and active area, we propose a new interpolation architecture using a symmetric three-input comparator. This ADC achieves 5.56 effective bits for input frequencies up to 220MHz at 1.6GS/s, and almost five effective bits for 660MHz input at 1.6GS/s. Peak INL and DNL are less than 0.5LSB and 0.45LSB, respectively. This ADC consumes 85mW from 1.8V at 1.6GS/s and occupies an active area of 0.27mm². It is fabricated in 0.18-μm CMOS.

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