A low-power rectifier for RF energy harvesting based on a novel operating principle is presented. The proposed diode rectifier integrates an external series inductor that resonates with the diode’s parasitic capacitances. This resonance enhances the electromotive force of the inductor, amplifying the RF input signal. As a result, the finite threshold voltage of silicon-based Schottky barrier diodes (SBDs) is effectively reduced, improving their sensitivity to weak environmental RF signals. Prototype rectifiers designed to operate at single and multiple resonant frequencies were fabricated using commercial discrete SBDs. These prototypes exhibited notably high RF-to-DC power conversion efficiencies at an RF input power of -20 dBm, achieving, for example, 38% efficiency at 700 MHz and an average efficiency of 21.6% across the 0.43-0.77 GHz band.

A novel gain and maximum oscillation frequency (fmax) enhancement method for GaN high-electron-mobility transistors (HEMTs) was developed using a standing wave-controlled gate (SC-gate). By intentionally modifying the fingertip termination condition, drastic gain and fmax improvements were achieved in the millimeter-wave frequency band without changing the manufacturing process of the GaN HEMTs. This study reviews the SC-gate technology and previous prototype evaluation results and reports additional analysis results. Furthermore, a W-band amplifier, MMIC, was designed and fabricated based on the S-parameter measurement data of the SC-gate GaN HEMT. The maximum available gain (MAG) of the SC-gate GaN HEMT used in this amplifier MMIC was 10 dB at 80 GHz, whereas the MAG in a conventional GaN HEMT without an SC-gate was 4.5 dB. The maximum gain of the fabricated amplifier MMIC was 6.3 dB at 80.6 GHz. This value is higher than that of the conventional GaN HEMT, which confirms the effectiveness of the SC-gate technology in the W band.

Two-dimensional electron gases (2DEGs) are essential not only for modern electronics but also for the advancement of next-generation communication technologies and quantum computing. Here, we report a non-contact method for characterizing material parameters of 2DEGs using circularly polarized TE_11n modes. By developing an excitation method utilizing a circular patch antenna with an adjustable coupling hole, we enable the use of higher-order modes up to TE₁₁₇, while minimizing the effects of cylindrical symmetry breaking. This method is demonstrated by measuring the magnetic field dependence of microwave conductivities in a GaAs/AlGaAs heterojunction at 300 K and 77 K. The electron mobility obtained by fitting to the Drude model is in good agreement with the results from standard Hall measurements. Additionally, the signature of cyclotron resonance is clearly observed at 77 K, and the effective electron mass is successfully estimated. The present method could accelerate fundamental research and device development using various 2DEGs.

This paper presents a millimeter-wave transceiver front-end (FE) circuit including a power amplifier (PA), a low noise amplifier equipped with phase inverter (LNA-PI), and a transmission/reception switch (TRX-SW) fabricated in 0.13-μm SiGe BiCMOS. The TRX-SW is configured as the output matching network for the PA in TX mode and as the input matching network for the LNA-PI in RX mode. The PA is implemented using a three stacked transistors architecture to provide high output power. Measurements of the FE in TX mode demonstrate peak S₂₁ of 33.0 dB at 29.9 GHz, S₂₁ 3-dB bandwidth (BW_-3dB) of 14.5 GHz from 18.0 to 32.5 GHz, saturated output power above 21 dBm, and power-added efficiency of 16.9 to 20.5% from 24 to 30 GHz. The PA achieves a competitive ITRS FoM of 96.3. In RX mode, the FE demonstrate peak S₂₁ of 23.4 dB at 20.0 GHz, S₂₁ BW_-3dB of 14.6 GHz from 18.2 to 32.8 GHz, and noise figure lower than 4 dB. The PI shows 180° phase shift within 10% error.

This paper proposes a design method for a decoupling network between antennas using a patch antenna array as a resonator, aimed at reducing network components. A key challenge in utilizing a patch antenna array as a resonator is the narrow spacing between transmission admittance inversion poles between antennas, leading to narrowband isolation. To address this issue, the study focused on the phase of even and odd modes of the patch antenna and successfully widened the spacing between the inversion poles of the transmission admittance by connecting a transmission line of appropriate length to the antenna. As a result, isolation with two transmission zeros was achieved without the need for an external resonator.

In this paper, we propose a sensor node using a unidirectional harmonic antenna that can acquire remote sensor information without complex digital circuits. The antenna suitable for the harmonic sensor node is characterized by utilizing a wideband E-shaped element to suppress pattern degradation at harmonic frequencies. First, through basic investigations where the sensor is modeled as a variable voltage source, we demonstrate that sensor voltage information can be remotely detected based on the transmission zero frequency. Next, using a sensor node incorporating a temperature sensor and energy harvesting circuit as an example, we show that the temperature in a remote location can be detected from the stopband frequency, thereby verifying the effectiveness of the proposed method. These findings are validated through harmonic balance analysis, electromagnetic field simulations, and RF circuit simulations.

Silicon spin qubits are a promising technology for scalable quantum computing, leveraging their inherent compatibility with CMOS integration process. However, as the number of silicon spin qubits increases, the exponential growth in signal cables required to control qubits within a dilution refrigerator become a significant bottleneck, along with the thermal inflow from external control systems. In addition, the implementation of signal wiring for qubit chips with a large number of I/O pads and internal heat generation of qubits themselves are also barriers to scale-up. To address these issues, we have developed cryogenic CMOS (Cryo-CMOS) analog circuits and advanced chip packaging techniques at deep cryogenic temperatures inside the refrigerator. These techniques enable the implementation of extensive signal wiring while suppressing heat generation, contributing to the realization of large-scale silicon spin qubit control. In this paper, we introduce cryogenic analog circuit designs including digital-to-analog converter (DAC) and analog-to-digital converter (ADC) for biasing spin qubits and acquiring their environmental data, respectively, with a focus on low power consumption and small area to meet space and power budget within the refrigerator. Furthermore, we introduce cryogenic flip-chip packaging techniques using silicon interposer and Cu-Cu bonding technology to enhance heat dissipation as examples of packaging strategies for installing large-scale qubit chips. These proposed techniques have been implemented as prototype chips, and their effectiveness has been demonstrated through cryogenic experiments using refrigerators.

Radio frequency (RF) integrated circuits for wireless applications began evolving in the 1990s, with the second generation of mobile phones as the primary application. The wireless local area network (WLAN), which began in the 2000s, and the fourth-generation mobile phone (smart phone), which began in the 2010s, have greatly expanded the transmission volume. The fifth generation of cell phones, which began in the 2020s, expanded the adaptive band to the millimeter wave band. The 6th generation mobile phones, which are expected to start in the 2030s, will continue to evolve to higher frequency bands, including sub-THz, for further expansion of transmission capacity. After the 4th generation, the application is not only for mobile phones but also for the IoT and other applications. Therefore, the required characteristics are also diverse, including broadband high-capacity transmission and narrow bandwidth low power consumption. This paper describes the evolution of integrated circuits for wireless applications, focusing on data communications, especially on high-capacity applications.

An energy-efficient 2-read/write (2RW) dual-port (DP) SRAM with a new disturbance aware replica scheme has been demonstrated. This scheme aims to generate internal critical timing signals for sense-enable (SE) triggers and wordline (WL) negating paths during the readout operation. By placing individual replica circuits for each port, appropriate internal delays are generated self-adjustably, whether accessing same-row or different-row. Even when the two clock inputs have different phases and frequencies, the proposed replica circuit effectively generates internal timings by mimicking the discharge speeds of each bitline (BL) using replica 8T DP bitcells. A prototype of a 256-kbit DP SRAM macro has been implemented in 90 nm logic CMOS technology. Measurement results show that the dynamic power consumption in the cell array is reduced by 16.6% compared to the conventional replica scheme at a typical supply voltage of 1.2 V and room temperature.

A cryogenic analog controller (CAC) for a silicon quantum computer using a spin qubit is presented in this paper, which operates on 4-K plate in a dilution refrigerator to suppress heat flow to qubits and latency. An RF pulse generator is a key for precise control of a spin qubit in CAC, which is required to generate 20-GHz pulse with low phase error. A low-noise LO and calibrations for DC offset and IQ imbalance are implemented in the pulse generator. LO includes LDO operating at weak inversion region and transformer coupled VCO cores to suppress flicker noise. A BGR operating at weak inversion region is also applied to supply low-noise bias voltage. CAC including the pulse generator is fabricated in 40-nm CMOS process. Low LO jitter of 137.4 fs, -59.7-dBc LO leakage, 67.7-dB IRR and 388-nJ energy per quantum operation have been achieved with the proposed 20-GHz LO and calibrations, resulting in 99.93-% fidelity.

This paper presents a CMOS full-wave switching rectifier capable of mixer operation. The proposed CMOS switching rectifier allows DC power generation and frequency conversion without a power supply. The proposed CMOS switching rectifier using a center-tapped balun produces DC power with 40.7% efficiency, while at the same time providing frequency up-conversion with -16.4 dB and down-conversion with -10.8 dB. The size of the chip is 0.286 mm², and four chips are mounted on the phased-array antenna board. The board can be used as a wirelessly powered relay transceiver, and the relay transceiver can be driven without an external power supply. In TX mode, the beamwidth is narrower than that of a common phased-array transceiver, but it is capable of beam steering from -45 to 45 degrees. On the other hand, in RX mode, the wide beamwidth allows the proposed relay transceiver to receive from a wide range without changing the phase shifter settings. The measured EVM values are -27.4 dB for TX mode and -27.5 dB for RX mode with a 400-MHz 64QAM OFDMA-mode signal (5G NR, MCS 17).

Low-noise, low-current consumption, and high-linearity 920-MHz fully-integrated cascode LNA operated under moderate-inversion region is presented. To obtain low-noise characteristics using an integrated poor-Q-factor on-chip inductor, a transistor operating under moderate inversion was found to be optimal since the inductance of the input inductor can be reduced. Furthermore, the moderate inversion operation presents low current consumption. However, the odd-order transconductance of the MOSFET operating under the moderate-inversion region induced poor linearity, which improved the gate width and gate bias optimization of the cascode MOSFET. The measurement results include an |s₂₁| of 14.0 dB, NF of 2.10 dB, and -5.2 dBm IIP3 with current consumption of 1.6 mA. The process technology used in this study was the TSMC 180 nm CMOS technology.

The growing interest in interleaved digital-to-analog converters (DACs) has led to numerous developments and designs, while extending interleaving factors poses several challenges. This research presents a hybrid segment architecture for expanding the number of channels in time-interleaved (TI)-DACs, addressing critical limitations of existing architectures. Our architecture incorporates a pre-filter, a single-stage analog multiplexer, and an output combiner, enabling improved performance and compromising bandwidth and usable output swing. In addition, a comprehensive system-level analysis is conducted in this paper to evaluate the performance of different TI-DAC architectures. The simulation result highlights the effectiveness of the hybrid architecture in achieving superior SNR with sufficient bandwidth and overcoming the challenges of channel number extension.