This paper proposes the continuous-time modeling and analysis methods for a hysteretic buck DC-DC converter to examine its frequency characteristics (f-characteristics) and transient response. Determining the small-signal transfer function to derive the f-characteristics has been challenging due to the hysteretic behavior of the comparator. In this paper, the hysteretic comparator is modeled as an amplifier with a delay time between the input exceeding the hysteresis window boundary and the output state change, and with a voltage gain defined as the ratio between the comparator’s output voltage change and the voltage difference of both input terminals during transition. The delay time is calculated based on the f-characteristics of the designed comparator circuits, and the voltage gain is determined using this delay time and the slew rate of the input signal. Subsequently, the overall small-signal transfer function and frequency characteristics are determined. It is also demonstrated that the proposed model accurately predicts the transient response when the load current changes. To verify the proposed modeling and analysis methods, a hysteretic buck DC-DC converter was designed and circuit-simulated using device parameters from a 0.18 µm CMOS process. The simulation results closely matched the calculated frequency characteristics and the transient response.

A load voltage estimation and regulation system for wireless power transfer circuits exploiting only primary-side control is proposed. The proposed system provides regulated load voltage independent of load and coupling conditions, using neither a secondary-side controller nor an external coil for intercommunication, as required in conventional systems. Adaptive frequency control based on a phase-locked loop technique enables the estimation of load voltage using only the electric parameters measurable on the primary side. Some formulas for voltage estimation and for designing a two-port matching circuit on the secondary side to maximize power transfer efficiency are derived. The versatile and explicit design formulas allow designers to easily determine circuit parameters to theoretically maximize efficiency corresponding to the specifications of each application. It is confirmed that a prototype system implemented on an one-coin-sized printed circuit board regulates the load voltage for several values of load and coupling coefficient.

In this paper we present a simple while comprehensive analytical design procedure for distributed amplifiers. Distributed amplifiers are attractive for designers due to their wideband capability. When designing a distributed amplifier, the first question that comes to mind is how wide the bandwidth can be. This paper answers this question by using the self-matching and low-pass properties of a distributed amplifier. Self-matching property of a distributed power amplifier is an interesting point that distinguishes it from other types of power amplifiers that are usually based on input and output matching networks. Here the estimation of the bandwidth of a distributed amplifier structure is discussed. The equations that are used in this paper can bring good insight and they can assist designers. Furthermore, we have explained the frequency behavior of a tapered distributed amplifier analytically for the first time. In order to validate the approach presented here, we have used published designs including our previously published design as practical examples. The flowchart of the design procedure is also provided.

We introduce “GNN-Opt,” a method that adapts “DNN-Opt’s” machine learning approach for analog circuit design, particularly op-amp sizing. By utilizing Graph Neural Networks, GNN-Opt demonstrates superior efficiency in transferring design knowledge across similar topologies, accelerating to achieve higher FoM with same simulation times.

We consider a nonlinear discrete-time system and a control specification including safety properties. In general, there exists a computation delay to compute a control input in a controller and the delay degrades control performances. To compensate the computation delay, we propose a safe controller using Mita’s method and the shield synthesis, where the satisfaction of the safety properties is decided using a high-order control barrier function. First, we show an effect of the computation delay on the relative degree of the system. Next, we show the reduction of the number of functions that specify the high-order control barrier function. Finally, we propose a safe controller consisting of a predictor, a controller, and a shield. Then, we illustrate the proposed method on safe control of mobile robots.

Service-Oriented Architecture (SOA) is an information system architecture. In SOA, the problem of synthesizing the concrete model from an abstract specification is known as the Choreography Realization Problem (CRP). So far, we proposed to use event structures as a modeling formalism; we studied conflict reduction of event structures to check the realizability of a choreography. In this paper, we study the method to generate event structure from choreography.

Elderly action recognition is a more challenging task due to the fact that elderly individuals move with small amplitude and long duration of actions. There are two pivotal issues that warrant further exploration including the development of enhanced temporal feature representations and the expansion of convolutional models’ capacity to capture long-range temporal features. In this paper, we propose a novel Skeleton Temporal Fusion Graph Convolutional Network (STF-GCN) for skeleton-based elderly action recognition, which effectively models advanced temporal feature representations. More specifically, the STF-GCN employs three encoding strategies to integrate two types of temporal feature representations. These strategies are designed to capture the intricacies of motion dynamics and the subtleties in action variations, enabling a more accurate and robust recognition of elderly actions. Furthermore, we propose a Skeleton Temporal Fusion (STF) module to highlight the temporal feature representations, employing a structure that alternates between large and small kernel convolutions to achieve various effective receptive fields. The integration of large kernel convolutions allows our model to perceive an expanded temporal context, enhancing its ability to deeply understand action dynamics. Our evaluation demonstrates that the STF-GCN achieves state-of-the-art performance on the largest elderly dataset, ETRI-Activity3D. Additionally, more extensive experimental results show that the STF-GCN is also comparable to other methods in general action recognition tasks.

A vector product Hopfield network (VPHN) is a 3-D Hopfield model. A VPHN provides excellent noise tolerance. Since projection rule is not available, it is not applicable for large numbers of data. Vector product appears in the multiplication of quaternions. In this work, the VPHNs are extended to the quaternionic VPHNs (QVPHNs). The projection rule is available for the QVPHNs. We evaluate the QVPHNs by computer simulations and show that they provide excellent noise tolerance.

Considering the problem that the vector speed control system of permanent magnet synchronous motor (PMSM) is susceptible to uncertainties such as load disturbances, a model-free control strategy based on terminal second-order sliding mode (TSOSM-MFC) is proposed. First, the mathematical model of PMSM is analysed and processed, and the corresponding ultra-local model of the system is summarised; then, the model-free terminal sliding mode speed controller is designed according to the ultra-local model of the system, and the chattering phenomenon in the system is suppressed by designing the second-order sliding mode reaching law (SOSMRL). Then, the sliding mode disturbance observer (SMDO) is designed to estimate the unknown part of the ultra-local model and compensate the speed loop to improve the robust performance of the system. Finally, the feasibility and effectiveness of the proposed control method are verified by simulation.

This paper analyzed and verified the condition for obtaining the maximum output power with an 85 kHz class-D half-bridge zero-voltage-switching (ZVS) inverter. The shunt capacitance in the class-D half-bridge ZVS inverter is formed by nonlinear parasitic capacitance and linear external capacitors. The design equation of the shunt capacitance is derived. For verification, two class-D half-bridge inverters are designed with Si-MOSFETs and SiC-MOSFETs in four specifications. The simulated and experimental waveform verified the validity of the design procedure for achieving the ZVS operation, and the measured result verified the analysis of output power characteristics with good consistency. Furthermore, the relationship between the maximum output power and parasitic capacitance is analyzed. It is clarified that the power MOSFET with smaller parasitic capacitance can obtain higher maximum output power. By comparing the maximum output power between the Si-MOSFET and SiC-MOSFET, it is indicated that the SiC-MOSFET with smaller parasitic capacitance can obtain higher maximum output power than Si-MOSFET, verifying the condition for obtaining the maximum output power.

Large-scale image pre-training models have recently demonstrated strong representation capabilities in spatial information contexts. Prior works apply these models to video action recognition through fully fine-tuning, which is expensive and resource-intensive. To reduce computational costs, some studies have shifted their focus to efficient parameter fine-tuning methods. However, existing efficient fine-tuning methods lack exploration of multi-scale information in videos. In this work, the Multi-scale spatio-temporal Adapter (MST-Adapter) is proposed for parameter-efficient Image-to-Video transfer learning. By freezing the pretrained models and adding the lightweight adapters, we only need to update few parameters, which is highly efficient. In addition, extensive experiments on two video action recognition benchmarks show that our method can learn high-quality video spatio-temporal representations and achieve competitive or even better performance than prior works.

The quality detection of copper alloys plays a crucial role in enhancing the factory’s economic and production efficiency, particularly in addressing surface defects and ensuring component size and specification accuracy. This paper proposes a deep learning-based quality detection method for detecting the defect on the surfaces of copper alloy components, encompassing both surface defect detection and external dimensional quality assessment. For defect detection, the method achieves an accuracy of 94% with an average detection time of 29 ms. In dimensional quality detection, the accuracy reaches 96%, with an average detection time of 3 seconds. Validation confirms that this deep learning-based method significantly improves the factory’s detection efficiency.

The deep learning method has been proven to be perfect in the field of multi-ship formation (MSF) recognition for high-frequency surface wave radar (HFSWR). However, the range-Doppler (RD) images of MSF are not always available in large quantities for training. And there is diversification in formation styles. In this paper, we propose a signal processing method for HFSWR formation recognition, which performs RD imaging through coherent accumulation and motion compensation. In the Doppler profile, the peaks are equal to sub-targets. The experiments based on actual RD background verify the feasibility and robustness of the proposed method.

SPECK is a family of lightweight block ciphers. While Sun et al.’s evaluation of SPECK’s differential characteristics was the most effective, it left room for further analysis over longer rounds. In this paper, we use a SAT-based search algorithm to analyze SPECK48, SPECK96, and SPECK128, presenting optimal differential characteristics up to 19, 15, and 11 rounds, respectively. We also explore the best characteristics up to 20 rounds for SPECK48, 18 rounds for SPECK96, and 20 rounds for SPECK128.

In this letter, we prove that binary cycle codes constructed from simple connected graphs have optimal stopping redundancy. For such a code, we also obtain a full-rank parity-check matrix whose number of minimum-size stopping sets is equal to the number of minimum-weight codewords of the code.