Adaptive voltage scaling is a promising approach to overcome manufacturing variability, dynamic environmental fluctuation, and aging. This paper focuses on error prediction based adaptive voltage scaling (EP-AVS) and proposes a mean time to failure (MTTF) aware design methodology for EP-AVS circuits. Main contributions of this work include (1) optimization of both voltage-scaled circuit and voltage control logic, and (2) quantitative evaluation of power saving for practically long MTTF. Experimental results show that the proposed EP-AVS design methodology achieves 38.0% power saving while satisfying given target MTTF.
A programmable analog calculation unit (ACU) is designed for vector computations in continuous-time with compact circuit scale. From our early study, it is feasible to retrieve arbitrary two-variable functions through support vector regression (SVR) in silicon. In this work, the dimensions of regression are expanded for vector computations. However, the hardware cost and computing error greatly increase along with the expansion of dimensions. A two-stage architecture is proposed to organize multiple ACUs for high dimensional regression. The computation of high dimensional vectors is separated into several computations of lower dimensional vectors, which are implemented by the free combination of several ACUs with lower cost. In this manner, the circuit scale and regression error are reduced. The proof-of-concept ACU is designed and simulated in a 0.18µm technology. From the circuit simulation results, all the demonstrated calculations with nine operands are executed without iterative clock cycles by 4960 transistors. The calculation error of example functions is below 8.7%.
A low voltage stochastic flash ADC (analog-to-digital converter) is presented, with an inverter-based comparative unit which is used to replace comparator for comparison. Aiming at the low voltage and low power consumption, a key of our design is in the simplicity of the structure. The inverter-based comparative unit replacing a comparator enables us to decrease the number of transistors for area saving and power reduction. We insert the inverter-chain in front of the comparative unit for the signal stability and discuss an appropriate circuit structure for the resolution by analyzing three different ones. Finally, we design the whole stochastic flash ADC for verifying our idea, where the supply voltage can go down to 0.6V on the 65nm CMOS process, and through post-layout simulation result, we can observe its advantage visually in voltage, area and power consumption.
Due to progressing process technology, yield of chips is reduced by timing violation caused by delay variation of gates and wires in fabrication. Recently, post-silicon delay tuning, which inserts programmable delay elements (PDEs) into clock trees before the fabrication and adjusts the delays of the PDEs to recover the timing violation after the fabrication, is promising to improve the yield. Although post-silicon delay tuning improves the yield, it increases circuit area and power consumption since the PDEs are inserted. In this paper, a PDE structure is taken into consideration to reduce the circuit area and the power consumption. Moreover, a delay selection algorithm, and a clustering method, in which some PDEs are merged into a PDE and the PDE is inserted for multiple registers, are proposed to reduce the circuit area and the power consumption. In computational experiments, the proposed method reduced the circuit area and the power consumption in comparison with an existing method.
In this paper, to make asynchronous circuit design easy, we propose a conversion method from synchronous Register Transfer Level (RTL) models to asynchronous RTL models with bundled-data implementation. The proposed method consists of the generation of an intermediate representation from a given synchronous RTL model and the generation of an asynchronous RTL model from the intermediate representation. This allows us to deal with different representation styles of synchronous RTL models. We use the eXtensible Markup Language (XML) as the intermediate representation. In addition to the asynchronous RTL model, the proposed method generates a simulation model when the target implementation is a Field Programmable Gate Array and a set of non-optimization constraints for the control circuit used in logic synthesis and layout synthesis. In the experiment, we demonstrate that the proposed method can convert synchronous RTL models specified manually and obtained by a high-level synthesis tool to asynchronous ones.
VLSIs that perform signal processing near infrared sensors cooled to ultra-low temperature are demanded. Delay test of those chips must be executed at ultra-low temperature while functional test could be performed at room temperature as long as hold timing errors do not occur. In this letter, we focus on the hold timing violation and evaluate the feasibility of functional test of ultra-low temperature circuits at room temperature. Experimental evaluation with a case study shows that the functional test at room temperature is possible.
We have developed a novel array configuration based on the combination of sum and difference co-arrays. There have been many studies on array antenna configurations that enhance the degree of freedom (DOF) of an array, but the maximum DOF of the difference co-array configuration is often limited. With our proposed array configuration, called “sum and difference composite co-array”, we aim to further enhance the DOF by combining the concept of sum co-array and difference co-array. The performance of the proposed array configuration is evaluated through computer simulated beamforming*.
The compressive sensing has been applied to develop an effective framework for simultaneously localizing multiple targets in wireless sensor networks. Nevertheless, existing methods implicitly use analog measurements, which have infinite bit precision. In this letter, we focus on off-grid target localization using quantized measurements with only several bits. To address this, we propose a novel localization framework for jointly estimating target locations and dealing with quantization errors, based on the novel application of the variational Bayesian Expectation-Maximization methodology. Simulation results highlight its superior performance.
The symbol flipping decoding algorithms based on prediction (SFDP) for non-binary LDPC codes perform well in terms of error performances but converge slowly when compared to other symbol flipping decoding algorithms. In order to improve the convergence rate, we design new flipping rules with two phases for the SFDP algorithms. In the first phase, two or more symbols are flipped at each iteration to allow a quick increase of the objective function. While in the second phase, only one symbol is flipped to avoid the oscillation of the decoder when the objective function is close to its maximum. Simulation results show that the SFDP algorithms with the proposed flipping rules can reduce the average number of iterations significantly, whereas having similar performances when compared to the original SFDP algorithms.
A physical-layer network coding (PNC) scheme is developed using serially concatenated continuous phase modulation (SCCPM) with symbol interleavers in a two-way relay channel (TWRC), i.e., SCCPM-PNC. The decoding structure of the relay is designed and the corresponding soft input soft output (SISO) iterative decoding algorithm is discussed. Simulation results show that the proposed SCCPM-PNC scheme performs good performance in bit error rate (BER) and considerable improvements can be achieved by increasing the interleaver size and number of iterations.