In this paper, horizontal (where an opamp is shared in two adjacent stages) and vertical (where an opamp is shared across two paths) opamp sharing techniques for a two-path band-pass (BP) ΔΣ modulator are described, and input-feedforward two-path fourth-order BP ΔΣ modulators that have only two opamps are proposed. The proposed modulators are based on the horizontal or vertical opamp sharing technique. They can be realized with both a summation circuit using a switched capacitor (SC) network and a second-order high-pass filter (HPF) with a horizontal shared opamp or a double-sampling first-order HPF with a vertical shared opamp, which are based on an SC first-order HPF with an opamp. These techniques can reduce the number of opamps with no additional component and the chip area as well as realize lower power consumption.

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This paper describes 10-bit, 80-MSample/s pipelined A/D converters for wireless-communication terminals. To reduce power consumption, we employed the I/Q amplifier sharing technique [1] in which an amplifier is used for both I and Q channels. In addition, common-source, pseudo-differential (PD) amplifiers are used in all the conversion stages for further power reduction. Common-mode disturbances are removed by the proposed common-mode feedforward (CMFF) technique without using fully differential (FD) amplifiers. The converter was implemented in a 90-nm CMOS technology, and it consumes only 24mW/ch from a 1.2V power supply. The measured SNR and SNDR are 58.6dB and 52.2dB, respectively.

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This paper proposes useful circuit structures for achieving a low-voltage/low-power pipelined ADC based on switched-opamp architecture. First, a novel unity-feedback-factor sample-and-hold which manipulates the features of switched-opamp technique is presented. Second, opamp-sharing is merged into switched-opamp structure with a proposed dual-output opamp configuration. A 0.8-V, 9-bit, 10-Msample/s pipelined ADC is designed to verify the proposed circuit. Simulation results using a 0.18-μm CMOS 1P6M process demonstrate the figure-of-merit of this pipelined ADC is only 0.71pJ/step.

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This paper proposes a performance model for design of pipelined analog-to-digital converters (ADCs). This model includes the effect of overdrive voltage on the transistor, slewing of the operational amplifier, multi-bit structure of multiplying digital to analog converter (MDAC) and technology scaling. The conversion frequency of ADC is improved by choosing the optimum overdrive voltage of the transistor, an important consideration at smaller design rules. Moreover, multi-bit MDACs are faster than the single-bit MDACs when slewing occurs during the step response. The performance model of pipelined ADC shown in this paper is attractive for the optimization of the ADC's performances.

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This paper discusses the input range limitation problem in a track-and-hold circuit and the compensation method using a bootstrapped switch. A bootstrapped switch with an additional control circuit is proposed to compensate charge loss in conventional bootstrapped switch circuit. Simulation results using 0.18-μm CMOS process parameters show that the proposed circuit reduces the bootstrap capacitance down to 25% for the conventional circuit.

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This paper presents an automatic adjustment of the transfer function of phase locked loop (PLL). The time constants and the gain factor of the transfer function are adjusted without opening the loop of PLL. The time constant adjustment is performed using a replica of the 1st order RC low pass filter and the gain factor is adjusted by detecting the open loop gain at the unity gain frequency. These adjustments are automatically carried out using a digitally controlled capacitance array and a digitally controlled charge pump. The proposed calibration can reduce the bandwidth error of ±30% to ±5% and the gain error of 7dB to 1dB.

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This paper presents a new open-loop phase shifter and frequency synthesizer which can be implemented by small hardware. In the proposed method the differential square wave is converted to a differential ramp. Then the cross points of two ramps are detected as the middle points of high or low durations and are recovered to full digital levels, for 90° shifting operation. 4-phases in 50MHz frequency can be generated by 3.5mW power consumption and 60μm×60μm area. All circuits have been simulated in 0.35μm CMOS technology.

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A high-speed triangular-modulated spread-spectrum clock generator using a fractional phase-locked loop is presented. The fractional division is implemented by a nested fractional topology, which is constructed from a dual-modulus divide-by-(N-1/16)/N divider to divide the VCO outputs as a first division period and a fractional control circuit to establish a second division period to cause the overall fractional division. The dual-modulus divider introduces a delay-locked-loop network to achieve phase compensation. Operating at the frequency of 3.2GHz, the measured peak power reduction is around 16dB for a deviation of 0.37% and a frequency modulation of 33kHz. The circuit occupies 1.4×1.4mm² in a 0.18-μm CMOS process and consumes 52mW.

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A design of a low-power CMOS ring oscillator for an application to a 13.56MHz clock generator in an implantable RFID tag is proposed. The circuit is based on a novel voltage inverter, which is an improved version of the conventional current-source loaded inverter. The proposed circuit enables low-power operation and low sensitivity of the oscillation frequency, f_OSC, to decay of the power supply V_DD. By employing a g_m-boosting subcircuit, power dissipation is decreased to 49μW at f_OSC=13.56MHz. The sensitivity of f_OSC to V_DD is reduced to -0.02 at f_OSC=13.56MHz thanks to the use of composite high-impedance current sources.

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A low-ripple diode charge-pump type AC-DC converter based on the Cockcroft-Walton diode multiplier is proposed for coilcoupled passive IC tags in this paper. This circuit is developed as a power supply for passive RFID tags with smart functions such as heart rate detection and/or body temperature measurement. The proposed circuit converts wirelessly induced power to a low-ripple DC voltage suitable for a 13.56MHz RFID tag. The proposed circuit topology and the principle of operation are explained and treated theoretically by using quasi-equivalent small-signal models. The proposed circuit was implemented on a PCB. And it was confirmed that the proposed circuit provides 3.3V DC with a ripple of less than 20mV when a 4V_p-p sinusoidal input is applied. Under this condition, the maximum output power is about 310μW. The measured results were in good agreement with theoretical and HSPICE simulation results.

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Since a receiver (RX) and a transmitter (TX) are operated simultaneously in a WCDMA transceiver, noise and intermodulation distortion performances of a low-noise amplifier (LNA) are degraded by a large leakage signal from the TX. The degradation of the distortion due to the large leakage signal from the TX has been reported in some previous works, but to our best knowledge, there are no reports about the degradation of noise figure (NF) in a LNA due to the large leakage signal from the TX. In this paper, a 900-MHz LNA for WCDMA terminal with high tolerance for a leakage signal from the TX is proposed. Suitable designs of an input matching circuit and a trap circuit are adopted to improve the tolerance for the leakage signal from the TX. The LNA using the proposed techniques is fabricated using SiGe-BiCMOS process. The measured degradation of NF due to the leakage signal from the TX is suppressed to only 0.12dB.

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Meeting the tough linearity and noise required by GSM and UMTS receivers in CMOS technology is challenging. A new IIP2 calibration technique based on canceling the second order nonlinearities of mixer, generated in the input RF transistors, is introduced. By using this technique about 22dB mixer IIP2 improvement is achieved. The proposed calibration circuit can be used in multi-standard mixer because of high bandwidth of the calibration circuitry. Moreover it can work with voltage supplies as low as 1V. Using this technique a multi-standard mixer supporting PCS, UMTS and IEEE802.11b-g is developed. The design is done in CMOS 65nm technology with 1.2V supply while it consumes about 7mA current.

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A multi-path structure is proposed for reduction in effect of digital substrate noise which degrades analog circuit performance. As an example low-pass filters are implemented in a 0.18-μm CMOS process. 11-dBm reduction in digital substrate noise is achieved as compared with a conventional structure.

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This paper addresses the on-resistance (R_on) extraction of the DMOS based driver in Power IC designs. The proposed method can extract R_on of a driver from its layout data for the arbitrarily shaped metallization patterns. Such a driver is usually composed of arbitrarily shaped metals, arrayed vias, and DMOS transistors. We use FEM to extract the parasitic resistance of the source/drain metals since its strong contribution to R_on. In order to handle the large design case and accelerate the extraction process, a domain decomposition with virtual terminal insertion method is introduced, which succeeds in extraction for a set of industrial test cases including those the FEM without domain decomposition failed in. For a layout in which the DMOS cells are regularly placed, a sub-domain reuse procedure is also proposed, which obtained a dramatic speedup for the extraction. Even without the sub-domain reuse, our method still shows advantage in runtime and memory usage according to the simulation results.

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This report describes an application of relaxation technique to the alternating direction implicit finite-difference time-domain (ADI-FDTD) method. The ADI-FDTD method is quite stable even when the CFL condition is not satisfied. However, the ADI-FDTD method is computationally more complicate than the conventional FDTD method and this method requires to solving the tri-diagonal matrix equation. Thus, this method may require more computational cost than the standard FDTD method due to the large scale tri-diagonal matrix solution corresponding to a large number of meshes. In this report, relaxation-based solution technique is discussed for the matrix solution and a simple numerical example is shown. As a result, it is confirmed that ADI-FDTD method with the relaxation technique is useful for the acceleration of the electromagnetic field simulation.

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In this paper, a frequency transformation for designing polyphase transfer functions is proposed. A modification to the bilinear LP-LP transformation, which assigns both stopband edges on negative frequency range whereas passband edges are on positive one, results polyphase transfer functions. Design examples show validity of the proposed method.

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Sampling clock jitter degrades the dynamic range of an analog-to-digital converter (ADC). In this letter, a low-power low-noise clock signal generator for ADCs is described. As a clock signal generator, a ring-VCO-based charge pump PLL is used to reduce power dissipation within a given jitter specification. The clock signal generator is fabricated on a CMOS chip with 200-MSPS 10-bit ADC. The measured results show that the ADC keeps a 60-MHz input bandwidth and 53-dB dynamic range and a next-generation mobile wireless terminal can be realized with the ADCs and the on-chip low-power clock generator.

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A method for extracting a sound signal from a particular area that is surrounded by multiple ambient noise sources is proposed. This method performs several fixed beamformings on a pair of small microphone arrays separated from each other to estimate the signal and noise power spectra. Noise suppression is achieved by applying spectrum emphasis to the output of fixed beamforming in the frequency domain, which is derived from the estimated power spectra. In experiments performed in a room with reverberation, this method succeeded in suppressing the ambient noise, giving an SNR improvement of more than 10dB, which is better than the performance of the conventional fixed and adaptive beamforming methods using a large-aperture microphone array. We also confirmed that this method keeps its performance even if the noise source location changes continuously or abruptly.

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This paper discusses the behavior of the second-order modes (Hankel singular values) of linear continuous-time systems under variable transformations with positive-real functions. That is, given a transfer function H(s) and its second-order modes, we analyze the second-order modes of transformed systems H(F(s)), where 1/F(s) is an arbitrary positive-real function. We first discuss the case of lossless positive-real transformations, and show that the second-order modes are invariant under any lossless positive-real transformation. We next consider the case of general positive-real transformations, and reveal that the values of the second-order modes are decreased under any general positive-real transformation. We achieve the derivation of these results by describing the controllability/observability Gramians of transformed systems, with the help of the lossless positive-real lemma, the positive-real lemma, and state-space formulation of transformed systems.

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Synthesis of quantum circuits is essential for building quantum computers. It is important to verify that the circuits designed perform the correct functions. In this paper, we propose an algorithm which can be used to verify the quantum circuits synthesized by any method. The proposed algorithm is based on BDD (Binary Decision Diagram) and is called X-decomposition Quantum Decision Diagram (XQDD). In this method, quantum operations are modeled using a graphic method and the verification process is based on comparing these graphic diagrams. We also develop an algorithm to verify reversible circuits even if they have a different number of garbage qubits. In most cases, the number of nodes used in XQDD is less than that in other representations. In general, the proposed method is more efficient in terms of space and time and can be used to verify many quantum circuits in polynomial time.

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As power consumption of the clock tree dominates over 40% of the total power in modem high performance VLSI designs, measures must be taken to keep it under control. One of the most effective methods is based on clock gating to shut off the clock when the modules are idle. However, previous works on gated clock tree power minimization are mostly focused on clock routing and the improvements are often limited by the given registers placement. The purpose of this work is to navigate the registers during placement to further reduce the clock tree power based on clock gating. Our method performs activity-aware register clustering that reduces the clock tree power not only by clumping the registers into a smaller area, but also by pulling the registers with the similar activity patterns closely to shut off the clock more time for the resultant subtrees. In order to reduce the impact of signal nets wirelength and power due to register clustering, we apply the timing and activity based net weighting in [14], which reduces the nets switching power by assigning a combination of activity and timing weights to the nets with higher switching rates or more critical timing. To tradeoff the power dissipated by the clock tree and the control signal, we extend the idea of local ungating in [6] and propose an algorithm of gate control signal optimization, which still sets the gate enable signal high if a register is active for a number of consecutive clock cycles. Experimental results on a set of MCNC benchmarks show that our approach is able to reduce the power and total wirelength of clock tree greatly with minimal overheads.

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Clustering L0 buffers is effective for energy reduction in the instruction memory caches of embedded VLIW processors. However, the efficiency of the clustering depends on the schedule of the target application. For improving the energy efficiency of L0 clusters, an operation shuffling is proposed, which explores assignment of operations for each cycle, generates various schedules, and evaluates them to find an energy efficient schedule. This approach can find energy efficient schedules, however, it takes a long time to obtain the final result. In this paper, we propose a new method to directly generate an energy efficient schedule without iterations of operation shuffling. In the proposed method, a compiler schedules operations using the result of the single operation shuffling as a constraint. We propose some optimization algorithms to generate an energy efficient schedule for a given L0 cluster organization. The proposed method can drastically reduce the computational effort since it performs the operation shuffling only once. The experimental results show that comparable energy reduction is achieved by using the proposed method while the computational effort can be reduced significantly over the conventional operation shuffling.

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In this paper, we present a new extension of the butterfly digraph, which is known as one of the topologies used for interconnection networks. The butterfly digraph was previously generalized from binary to d-ary. We define a new digraph by adding a signed label to each vertex of the d-ary butterfly digraph. We call this digraph the dihedral butterfly digraph and study its properties. Furthermore, we show that this digraph can be represented as a Cayley graph. It is well known that a butterfly digraph can be represented as a Cayley graph on the wreath product of two cyclic groups [1]. We prove that a dihedral butterfly digraph can be represented as a Cayley graph in two ways.

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This paper deals with redundant 3D mesh processor arrays using 1.5-track switches, considering track and switch faults together with processor faults. Four variants are defined based on the distributions of spare PEs, and arrays of three variants have the same PE redundancies among them, but the fabrication-time costs are different. We investigate in detail how the reliability of a total system changes according to the reliabilities of tracks and switches as well as PEs, and show the concrete values of M_t and M_s, when the reliability of array are almost the same even if its variant is changed, and when it is not so, respectively, where M_t and M_s are the ratio of the hardware complexities of a PE and a track, and that of a PE and a contact point of a switch, respectively. Other results which are effective basis for the design of fault-tolerant 3D PE arrays using 1.5-TSs are given.

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Burn-in is a widely used method to improve the quality of products or systems after they have been produced. In this paper, optimal burn-in procedures for a system with two types of failures (i. e., minor and catastrophic failures) are investigated. A new system surviving burn-in time b is put into field operation and the system is used under a warranty policy under which the manufacturer agrees to provide a replacement system for any system that fails to achieve a lifetime of at least w. Upper bounds for optimal burn-in time minimizing the total expected warranty cost are obtained under a more general assumption on the shape of the failure rate function which includes the bathtub shaped failure rate function as a special case.

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In 1997, M. Matsui proposed secret-key cryptosystems called MISTY 1 and MISTY 2, which are 8- and 12-round block ciphers with a 64-bit block, and a 128-bit key. They are designed based on the principle of provable security against differential and linear cryptanalysis. In this paper we present large collections of weak-key classes encompassing 2⁷³ and 2⁷⁰ weak keys for 7-round MISTY 1 and 2 for which they are vulnerable to a related-key amplified boomerang attack. Under our weak-key assumptions, the related-key amplified boomerang attack can be applied to 7-round MISTY 1 and 2 with 2⁵⁴, 2⁵⁶ chosen plaintexts and 2^55.3 7-round MISTY 1 encryptions, 2⁶⁵ 7-round MISTY 2 encryptions, respectively.

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Canetti et al. [5] showed that there exist signature and encryption schemes that are secure in the random oracle (RO) model, but for which any implementation of the RO (by a single function or a function ensemble) results in insecure schemes. Their result greatly motivates the design of cryptographic schemes that are secure in the standard computational model. This paper gives some new results on the RO methodology. First, we give the necessary and sufficient condition for the existence of a signature scheme that is secure in the RO model but where, for any implementation of the RO, the resulting scheme is insecure. Next, we show that this condition induces a signature scheme that is insecure in the RO model, but that there is an implementation of the RO that makes the scheme secure.

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A new subfamily of sequences with optimal correlation properties is constructed for the generalized Kasami set. A lower bound on the linear span is established. It is proved that with suitable choices of parameters, this subfamily has exponentially larger linear spans than either No sequences or TN sequences. A class of sequences with ideal autocorrelation is also proved to have large linear span.

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In this paper, we propose a method that recovers a smooth high-resolution image from several blurred and roughly quantized low-resolution images. For compensation of the quantization effect we introduce measurements of smoothness, Huber function that is originally used for suppression of block noises in a JPEG compressed image [Schultz & Stevenson '94] and a smoothed version of total variation. With a simple operator that approximates the convex projection onto constraint set defined for each quantized image [Hasegawa et al. '05], we propose a method that minimizes these cost functions, which are smooth convex functions, over the intersection of all constraint sets, i. e. the set of all images satisfying all quantization constraints simultaneously, by using hybrid steepest descent method [Yamada & Ogura '04]. Finally in the numerical example we compare images derived by the proposed method, Projections Onto Convex Sets (POCS) based conventinal method, and generalized proposed method minimizing energy of output of Laplacian.

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In this letter, a computational approach for solving cross-coupled algebraic Riccati equations (CAREs) is investigated. The main purpose of this letter is to propose a new algorithm that combines Newton's method with a gradient-based iterative (GI) algorithm for solving CAREs. In particular, it is noteworthy that both a quadratic convergence under an appropriate initial condition and reduction in dimensions for matrix computation are both achieved. A numerical example is provided to demonstrate the efficiency of this proposed algorithm.

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Based on the concept of sliding mode control, this paper investigates the upper bound covariance assignment with H_∞ norm and variance constrained problem for bilinear stochastic systems. We find that the invariance property of sliding mode control ensures nullity of the matched bilinear term in the system on the sliding mode. Moreover, using the upper bound covariance control approach and combining the sliding phase and hitting phase of the system design, we will derive the control feedback gain matrix G, which is essential to the controller u(t) design, to achieve the performance requirements. Finally, a numerical example is given to illustrate the control effect of the proposed method.

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The quality of the Side-information frame (S frame) influences significantly the rate-distortion performance in the Distributed Video Coding (DVC). In this letter, we propose an efficient Side-Information Frame Generator (SIFG). It considers smoothness constraints of both the motion vector field and spatial adjacent pixels. Simulation results show that the proposed techniques provide potential rate-distortion performance advantages. Besides, the fine visual quality of the S frame is obtained.

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For unitary space-time code (USTC), the impact of spatial correlation on error performance is investigated. A tighter and simpler upper bound is derived for generalized likelihood ratio test decoder. We establish that the spatial correlation does not change the diversity gain, whereas it degrades the error performance of USTC. Motivated by the precoding of space-time block code, we designed a precoder for USTC to handle the case of the joint transmit-receive correlation. Numerical results show that the degradation in performance due to spatial correlation can be considerably compensated by the proposed algorithm.

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This paper presents a simulation based method to predict the amount of frequency interference in a passive type RFID system. To judge occurrence of frequency interference, we use a parameter POI (probability of interference) that depends on several factors such as multiple access method, emission mask, the number of channel, etc. Due to its dependence on several factors, a Monte-carlo based simulation is suitably used. Through the simulation, we draw minimum separation distance between two readers and examine performance degradation due to aggregate interfering readers. Moreover, we present a reader deployment strategy based on the average POI of active readers operating in some area.

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In this paper, an energy-collection-based non-coherent IR-UWB receiver allowing low complexity and low power consumption is proposed for short range data communication. The proposed receiver consists of an on-the-fly integrator, a 1-bit digital sampler, a pre-processor and a digital symbol synchronizer. The on-the-fly integrator for energy collection and the 1-bit digital sampler reduce complexity of IR-UWB system. Furthermore, with a simple digital filter in the pre-processing unit, SNR and robustness of the receiver against time-varying channel are enhanced. Also the receiver complexity is diminished by a simple scheme of symbol synchronization based on rough time information about incoming pulses, not requiring exact timing information. The performance of the proposed receiver is simulated based on IEEE 802. 15. 4a channel model and the algorithms are implemented and verified on a FPGA.

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In this letter, we examine the linear complexity of some 3-ary sequences, proposed by No, of period 3ⁿ-1 (n=3ek, e, k integer) with the ideal autocorrelation property. The exact value of linear complexity k(6e)^w is determined when the parameter r=w∑i=13^e_i. Furthermore, the upper bound of the linear complexity is given when the other forms of the value r is taken. Finally, a Maple program is designed to illustrate the validity of the results.

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This paper introduces an adaptive low complexity preprocessing filter to improve the coding performance of seriously degraded video sequences that is caused by the additive noise. The additive noise leads to a decrease in coding performance due to the high frequency components. By incorporating local statistics and quantization parameter into filtering process, the spurious noise is significantly attenuated and coding efficiency is improved for given quantization step size. In order to reduce the complexity of the pre-processing filter, the simplified local statistics and quantization parameter are introduced. The simulation results show the capability of the proposed algorithm.

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