This paper introduces several techniques for achieving RF and analog CMOS circuits for wireless communication systems under ultra-low-voltage supply, such as 0.5V. Forward body biasing and inverter-based circuit techniques were applied in the design of a feedforward Δ-Σ A/D modulator operating with a 0.5V supply. Transformer utilization is also presented as an inductor area reduction technique. In addition, application of stochastic resonance to A/D conversion is discussed as a future technology.

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Recent advanced technology makes digital circuits small and the number of digital functional blocks that can be integrated on a single chip is increasing rapidly. On the other hand, reduction in the size of analog circuits has been insufficient. This means that the analog circuit area is relatively large, and reducing analog circuit area can be effective to make a low cost radio receiver. In this paper, a new wireless receiver architecture that occupies small analog area is proposed, and measured results of the core analog blocks are described. To reduce the analog area, a balanced 3-phase analog system is adopted and the functions of analog baseband filters and VGAs are moved to the digital domain. The test chip consists of a 3-phase downconverter and a 3-phase ADC. There is no analog baseband filter on the chip and the analog filter is assumed to be replaced with a digital filter. The downconverter and ADC occupy 0.28mm². The measured results show the possibility that the requirements for IMT-2000 are fulfilled even with a small chip area.

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In this paper, a single-chip dual-mode 8-band 130nm CMOS transceiver including A/D/A converters and digital filters with 312MHz LVDS interface is presented. For a transmitter chain, linear direct quadrature modulation architecture is introduced for both W-CDMA/HSDPA (High Speed Uplink Packet Access) and for GSM/EDGE. Analog baseband LPFs and quadrature modulators are commonly used both for GSM and for EDGE. For a direct conversion receiver chain, ABB (Analog Base-Band) blocks, i.e., LPFs and VGAs, delta-sigma A/D converters, and FIR filters are commonly used for W-CDMA/HSDPA (High Speed Downlink Packet Access) and GSM/EDGE to reduce chip area. Their characteristics can be reconfigured by register-based control sequence. The receiver chain also includes high-speed DC offset cancellers both in analog and in digital stage, and the self-contained AGC controller, whose parameters such as time constant are programmable to be free from DBB (Digital Base-Band) control. The transceiver also includes wide-range VCOs and fractional PLLs, an LVDS driver and receiver for high-speed digital interface of 312MHz. Measured results reveal that the transceiver satisfies 3GPP specifications for W-CDMA/HSPA (High Speed Packet Access) and GSM/EDGE.

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This paper proposes a voltage-to-current converter with nested feedback loop configuration to achieve high loop gain without reducing the bandwidth. Simulation results using 0.18-µm CMOS process parameters show that the proposed circuit has a good linearity performance. The simulated bandwidth is 350MHz. The THD improvement of the proposed circuit is more than 60dB compared to the one of a common gate circuit under a same total current consumption of 10.4mA.

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This paper proposes a new realization technique of image rejection function by noise-coupling architecture, which is used for a complex bandpass ΔΣAD modulator. The complex bandpass ΔΣAD modulator processes just input I and Q signals, not image signals, and the AD conversion can be realized with low power dissipation. It realizes an asymmetric noise-shaped spectra, which is desirable for such low-IF receiver applications. However, the performance of the complex bandpass ΔΣAD modulator suffers from the mismatch between internal analog I and Q paths. I/Q path mismatch causes an image signal, and the quantization noise of the mirror image band aliases into the desired signal band, which degrades the SQNDR (Signal to Quantization Noise and Distortion Ratio) of the modulator. In our proposed modulator architecture, an extra notch for image rejection is realized by noise-coupled topology. We just add some passive capacitors and switches to the modulator; the additional integrator circuit composed of an operational amplifier in the conventional image rejection realization is not necessary. Therefore, the performance of the complex modulator can be effectively raised without additional power dissipation. We have performed simulation with MATLAB to confirm the validity of the proposed architecture. The simulation results show that the proposed architecture can achieve the realization of image-rejection effectively, and improve the SQNDR of the complex bandpass ΔΣAD modulator.

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A 0.9-V 12-bit 40-MSPS pipeline ADC with I/Q amplifier sharing technique is presented for wireless receivers. To achieve high linearity even at 0.9-V supply, the clock signals to sampling switches are boosted over 0.9V in conversion stages. The clock-boosting circuit for lifting these clocks is shared between I-ch ADC and Q-ch ADC, reducing the area penalty. Low supply voltage narrows the available output range of the operational amplifier. A pseudo-differential (PD) amplifier with two-gain-stage common-mode feedback (CMFB) is proposed in views of its wide output range and power efficiency. This ADC is fabricated in 90-nm CMOS technology. At 40MS/s, the measured SNDR is 59.3dB and the corresponding effective number of bits (ENOB) is 9.6. Until Nyquist frequency, the ENOB is kept over 9.3. The ADC dissipates 17.3mW/ch, whose performances are suitable for ADCs for mobile wireless systems such as WLAN/WiMAX.

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This paper describes a flash ADC using interpolation (IP) and cyclic background self-calibrating techniques. The proposed IP technique that is cascade of capacitor IP and gate IP with dynamic double-tail latched comparator reduces non-linearity, power consumption, and occupied area. The cyclic background self-calibrating technique periodically suppresses offset mismatch voltages caused by static fluctuation and dynamic fluctuation due to temperature and supply voltage changes. The ADC has been fabricated in 90-nm 1P10M CMOS technology. Experimental results show that the ADC achieves SNDR of 6.07bits without calibration and 6.74bits with calibration up to 500MHz input signal at sampling rate of 600MSps. It dissipates 98.5mW on 1.2-V supply. FoM is 1.54pJ/conv.

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This paper describes an algorithm for Successive Approximation Register (SAR) ADCs with overlapping steps that allow comparison decision errors (due to, such as DAC incomplete settling) to be digitally corrected. We generalize this non-binary search algorithm, and clarify which decision errors it can digitally correct. This algorithm requires more SAR ADC conversion steps than a binary search algorithm, but we show that the sampling speed of an SAR ADC using this algorithm can be faster than that of a conventional binary-search SAR ADC—because the latter must wait for the settling time of the DAC inside the SAR ADC.

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The multiple-divide technique, using the multi-ratio frequency divider, has a possibility to improve FoM of VCO. This paper proposes a design optimization of LC-VCO using the multiple-divide technique. In the simulated results using 90-nm CMOS model parameters, the optimum frequency range, achieving better than -187.0dBc/Hz of FoM, can be extended from 6.5-12.5GHz to 1.5-12.5GHz. The proposed multiple-divide technique can provide a lower phase-noise, lower power consumption, smaller layout area of LC-VCO.

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An L-2L through-line de-embedding method has been verified up to millimeter wave frequency. The parasitics of the pad can be modeled from the L-2L through-line. Measurement results of the transmission lines and transistors can be de-embedded by subtracting the parasitic matrix of the pad. Therefore, the de-embedding patterns, which is used for modeling active and passive devices, decrease greatly and the chip area also decreases. A one-stage amplifier is firstly implemented for helping verifying the de-embedding results. After that a four-stage 60GHz amplifier has been fabricated in CMOS 65nm process. Experimental results show that the four-stage amplifier realizes an input matching better than -10.5dB and an output matching better than -13dB at 61GHz. A small signal power gain of 16.4dB and a 1dB output compression point of 4.6dBm are obtained with a DC current consumption of 128mA from a 1.2V power supply. The chip size is 1.5mm × 0.85mm.

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Capacitance charging modeling efficiently captures power supply currents in dynamic operations of a CMOS digital circuit and accurately expresses their interaction with on- and off-chip impedance networks. Derivation of such models is generally defined for combinational and sequential logic functions. Simulated substrate and power noises due to sequential logic operation show clear dependency on the size of circuits as well as the internal activity of logic gates. Furthermore, it is experimentally found that the inclusion of impedance networks of a silicon substrate, a package, and an evaluation board, is substantially effective to improve the accuracy of noise analysis. Quantitative correlation among simulation with on-chip noise measurements is demonstrated in a 90-nm 1.2-V CMOS technology.

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Substrate noise analysis has become increasingly important in recent LSI design. This is because substrate noise, which affects PLLs, causes jitter that results in timing error. Conventional analysis techniques of substrate noise are, however, impractical for large-scale designs that have hundreds of millions of transistors because the computational complexity is too huge. To solve this problem, we have developed a fast substrate noise analysis technique for large-scale designs, in which a chip is divided into multiple domains and the circuits of each domain are reduced into a macro model. Using this technique, we have designed a processor chip for use in the supercomputer (die size: 20mm × 21mm, frequency: 3.2GHz, transistor count: 350M). Computation time with this design is five times faster than that with a 1/3000 scale design using a conventional technique, while resulting discrepancy with measured period jitter is less than 15%.

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We propose the multi-domain adaptive learningthat enables us to find a point meeting possibly time-varying specifications simultaneously in multiple domains, e.g. space, time, frequency, etc. The novel concept is based on the idea of feasibility splitting — dealing with feasibility in each individual domain. We show that the adaptive projected subgradient method(Yamada, 2003) realizes the multi-domain adaptive learning by employing (i) a projected gradient operator with respect to a ‘fixed’ proximity function reflecting the time-invariant specifications and (ii) a subgradient projection with respect to ‘time-varying’ objective functions reflecting the time-varying specifications. The resulting algorithm is suitable for real-time implementation, because it requires no more than metric projections onto closed convex sets each of which accommodates the specification in each domain. A convergence analysis and numerical examples are presented.

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In this paper, we propose a novel stochastic gradient algorithm for efficient adaptive filtering. The basic idea is to sparsify the initial error vector and maximize the benefits from the sparsification under computational constraints. To this end, we formulate the task of algorithm-design as a constrained optimization problem and derive its (non-trivial) closed-form solution. The computational constraints are formed by focusing on the fact that the energy of the sparsified error vector concentrates at the first few components. The numerical examples demonstrate that the proposed algorithm achieves the convergence as fast as the computationally expensive method based on the optimization without the computational constraints.

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This paper proposes closed form solutions to the L₂-sensitivity minimization subject to L₂-scaling constraints for second-order state-space digital filters with real poles. We consider two cases of second-order digital filters: distinct real poles and multiple real poles. The proposed approach reduces the constrained optimization problem to an unconstrained optimization problem by appropriate variable transformation. We can express the L₂-sensitivity by a simple linear combination of exponential functions and formulate the L₂-sensitivity minimization problem by a simple polynomial equation. As a result, L₂-sensitivity is expressed in closed form, and its minimization subject to L₂-scaling constraints is achieved without iterative calculations.

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A novel method to efficiently synthesize hardware from a large behavioral description in behavioral synthesis is proposed. For a program with functions executable in parallel, this proposed method determines a behavioral partitioning which simultaneously minimizes the overall datapath area and the complexity of the controller while maximizing performance of a synthesized circuit by fully exploiting function-level parallelism of a behavioral description. This method is formulated as an integer programming problem. Experimental results demonstrate that this method leads to a shift of the explorable design space so that superior solutions which could not be explored by earlier work are included, showing the effectiveness of our proposed method.

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This paper considers replacement and maintenance policies for an operating unit which works at random times for jobs. The unit undergoes minimal repairs at failures and is replaced at a planned time T or at a number N of working times, whichever occurs first. The expected cost rate is obtained, and an optimal policy which minimizes it is derived analytically. The imperfect preventive maintenance (PM) model, where the unit is improved by PM after the completion of each working time, is analyzed. Furthermore, when the work of a job incurs some damage to the unit, the replacement model with number N is proposed. The expected cost rate is obtained by using theory of cumulative processes. Two modified models, where the unit is replaced at number N or at the first completion of the working time over time T, and it is replaced at T or number N, whichever occurs last, are also proposed. Finally, when the unit is replaced at time T, number N or Kth failure, whichever occurs first, the expected cost rate is also obtained.

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Digital fingerprinting is used to trace back illegal users, where unique ID known as digital fingerprints is embedded into a content before distribution. On the generation of such fingerprints, one of the important properties is collusion-resistance. Binary codes for fingerprinting with a code length of theoretically minimum order were proposed by Tardos, and the related works mainly focused on the reduction of the code length were presented. In this paper, we present a concrete and systematic construction of the Tardos's fingerprinting code using a chaotic map. Using a statistical model for correlation scores, the actual number of true-positive and false-positive detection is measured. The collusion-resistance of the generated fingerprinting codes is evaluated by a computer simulation.

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We consider the use of the additive white Gaussian noise channel to achieve information theoretically secure oblivious transfer. A protocol for this primitive that ensures the correctness and privacy for players is presented together with the signal design. We also study the information theoretic efficiency of the protocol, and some more practical issues where the parameter of the channel is unknown to the players.

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M-spotty byte error control codes are very effective for correcting/detecting errors in semiconductor memory systems that employ recent high-density RAM chips with wide I/O data (e.g., 8, 16, or 32bits). In this case, the width of the I/O data is one byte. A spotty byte error is defined as random t-bit errors within a byte of length b bits, where 1 le t ≤ b. Then, an error is called an m-spotty byte error if at least one spotty byte error is present in a byte. M-spotty byte error control codes are characterized by the m-spotty distance, which includes the Hamming distance as a special case for t =1 or t = b. The MacWilliams identity provides the relationship between the weight distribution of a code and that of its dual code. The present paper presents the MacWilliams identity for the m-spotty weight enumerator of m-spotty byte error control codes. In addition, the present paper clarifies that the indicated identity includes the MacWilliams identity for the Hamming weight enumerator as a special case.

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This paper represents a feedback artificial immune system (FAIS). Inspired by the feedback mechanisms in the biological immune system, the proposed algorithm effectively manipulates the population size by increasing and decreasing B cells according to the diversity of the current population. Two kinds of assessments are used to evaluate the diversity aiming to capture the characteristics of the problem on hand. Furthermore, the processing of adding and declining the number of population is designed. The validity of the proposed algorithm is tested for several traveling salesman benchmark problems. Simulation results demonstrate the efficiency of the proposed algorithm when compared with the traditional genetic algorithm and an improved clonal selection algorithm.

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We propose a surface profiling algorithm by white-light interferometry that extends sampling interval to twice of the widest interval among those used in conventional algorithms. The proposed algorithm uses a novel function called an in-phase component of an interferogram to detect the peak of the interferogram, while conventional algorithms used the squared-envelope function or the envelope function. We show that the in-phase component has the same peak as the corresponding interferogram when an optical filter has a symmetric spectral distribution. We further show that the in-phase component can be reconstructed from sampled values of the interferogram using the so-called quadrature sampling technique. Since reconstruction formulas used in the algorithm are very simple, the proposed algorithm requires low computational costs. Simulation results show the effectiveness of the proposed algorithm.

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Recently some attempts have been made in the literature to give simple proofs of Jury test for real polynomials. This letter presents a similar result for complex polynomials. A simple proof of Jury test for complex polynomials is provided based on the Rouché's Theorem and a single-parameter characterization of Schur stability property for complex polynomials.

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Disturbance attenuation for a class of time-delay systems is performed by a combined simple adaptive control (SAC) with a new configuration of disturbance observer (DOB). The nominal system results from the Pade approximation, which is in the form of a non-minimum phase LTI system. For the implementation of SAC and DOB, two parallel feedforward compensators (PFC) are designed with the inverses of PD- and PID-controller, respectively. Simulation results show the effectiveness of the proposed controller to compensate the disturbance response and uncertain delay time.

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We propose an extension method of quaternary low correlation zone (LCZ) sequence set with odd period. From a quaternary LCZ sequence set with parameters (N , M, L, 1), the proposed method constructs a new quaternary LCZ sequence set with parameters (2N, 2M, L, 2), where N is odd. If the employed LCZ sequence set in the construction is optimal, the extended LCZ sequence set becomes also optimal where N = kL, L > 4, and k >2.

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Context-based adaptive variable length coding (CAVLC) is an entropy coding scheme employed in H.264/AVC for transform coefficient compression. The CAVLC encodes levels of nonzero-valued coefficients. Then indicates their positions with run_before which is number of zeros preceding each nonzero coefficient in scan order. In H.264, the run_before is coded using lookup tables depending on number of zero-valued coefficients that have not been coded. This paper presents an improved run_before coding method which encodes run_before using tables taking both zero-valued and nonzero-valued coefficients into consideration. Simulation results report that the proposed method yields an average of 4.40% bit rate reduction for run_before coding over H.264 baseline profile with intra-only coding structure. It corresponds to 0.52% bit rate saving over total bit rate on average.

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This paper proposes an improved method of reversible data hiding with increased capacity. The conventional method determines whether to embed a data bit in an image block according to the statistics of pixels in that block. Some images have pixel statistics that are inadequate for data hiding, and seldom or never have data embedded in them. The proposed method modulates the statistics invertibility to overcome such disadvantages, and is also able to improve the quality of the image containing the hidden data using block-adaptive modulation. Simulationresults show the effectiveness of the proposed method.

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We present the Fuzzy Directional (FD) filter to remove impulse noise from corrupted colour images. Simulation results have shown that the restoration performance is better in comparison with other known filters.

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