In advance of network communication society by the internet, the way how to send data fast with a little loss becomes an important transportation problem. A generalized maximum flow algorithm gives the best solution for the transportation problem that which route is appropriated to exchange data. Therefore, the importance of the maximum flow algorithm is growing more and more. In this paper, we propose a Maximum-Flow Neural Network (MF-NN) in which branch nonlinearity has a saturation characteristic and by which the maximum flow problem can be solved with analog high-speed parallel processing. That is, the proposed neural network for the maximum flow problem can be realized by a nonlinear resistive circuit where each connection weight between nodal neurons has a sigmodal or piece-wise linear function. The parallel hardware of the MF-NN will be easily implemented.

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The optimization of nonlinear feedback fuzzy system using the product-sum-gravity method is described in this paper. The fuzzy control discussed here is the nonlinear feedback control in which the feedback laws are determined by IF-THEN type fuzzy production rules through product-sum-gravity method. To prove existence of optimal control, we applied compactness of a set of membership functions in L² space and continuity of the approximate reasoning, and prepared some propositions concerning product-sum-gravity method. By considering fuzzy optimal control problems as problems of finding the minimum (maximum) value of the integral cost (benefit) function on an appropriate set of membership functions, the existence of fuzzy optimal control is shown.

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In this paper, we propose a control method for the synchronization of chaotic systems that does not require the systems to be connected, unlike existing methods such as that proposed by Pecora and Carroll in 1990. The method is based on the reinforcement learning algorithm. We apply our method to two discrete-time chaotic systems with mismatched parameters and achieve M step delay synchronization. Moreover, we extend the proposed method to the synchronization of continuous-time chaotic systems.

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A new analog mismatch model in circuit level has been developed. MOS transistor's small signal parameters are modeled in term of their matching character for both strong- and weak-inversion operations. Mismatch analysis on basic CMOS amplifiers are conducted with proposed model and Monte Carlo SPICE simulations. We successfully derived simple analytical formula on performance mismatch for analog CMOS circuits, which is verified to be accurate in using actual analog circuit design, within an average error of less than 10%.

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Electrical modeling for surface-mount passive components is proposed. In order to accurately capture parasitic inductance, the proposed 2-port model accounts for surrounding ground layer configurations of the print circuit board (PCB) on which the component is mounted. Our model retains conventional modeling paradigm in which component suppliers provide their customers with simulation models characterized independently of the customers' PCB. We also present necessary corrections that compensate magnetic coupling between the separated models. Impedance and its anti-resonant frequency of two power distribution networks are experimentally analyzed being non-separated modeling as the reference. The proposed model achieved very good match with the reference result reducing 7-34% error of the conventional model to about 2%.

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A PN junction current model for advanced MOSFETs is proposed and implemented into HiSIM2, a complete surface-potential-based MOSFET model. The model includes forward diode currents and reverse diode currents, and requires a total of 13 model parameters covering all bias conditions. Model simulation results reproduce measurements for different device geometries over a wide range of bias and temperature values.

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Process variation is becoming a primal concern in timing closure of LSI (Large Scale Integrated Circuit) with the progress of process technology scaling. To overcome this problem, SSTA (Statistical Static Timing Analysis) has been intensively studied since it is expected to be one of the most efficient ways for performance estimation. In this paper, we study variation of output transition-time. We firstly clarify that the transition-time variation can not be expressed accurately by a conventional first-order sensitivity-based approach in the case that the input transition-time is slow and the output load is small. We secondly reveal quadratic dependence of the output transition-time to operating margin in voltage. We finally propose a procedure through which the estimation of output transition-time becomes continuously accurate in wide range of input transition-time and output load combinations.

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Complex bandpass ΔΣAD modulators can provide superior performance to a pair of real bandpass ΔΣAD modulators of the same order. They process just input I and Q signals, not image signals, and AD conversion can be realized with low power dissipation, so that they are desirable for such low-IF receiver applications. This paper proposes a new architecture for complex bandpass ΔΣAD modulators with cross-noise-coupled topology, which effectively raises the order of the complex modulator and achieves higher SQNDR (Signal to Quantization Noise and Distortion Ratio) with low power dissipation. By providing the cross-coupled quantization noise injection to internal I and Q paths, noise coupling between two quantizers can be realized in complex form, which enhances the order of noise shaping in complex domain, and provides a higher-order NTF using a lower-order loop filter in the complex ΔΣAD modulator. Proposed higher-order modulator can be realized just by adding some passive capacitors and switches, the additional integrator circuit composed of an operational amplifier is not necessary, and the performance of the complex modulator can be effectively raised without more power dissipation. We have performed simulation with MATLAB to verify the effectiveness of the proposed architecture. The simulation results show that the proposed architecture can achieve the realization of higher-order enhancement, and improve SQNDR of the complex bandpass ΔΣAD modulator.

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This paper proposes spread-spectrum clock modulation algorithms for EMI reduction in digitally-controlled DC-DC converters. In switching regulators using PWM, switching noise and harmonic noise concentrated in a narrow spectrum around the switching frequency can cause severe EMI. Spread-spectrum clock modulation can be used to minimize EMI. In conventional switching regulators using analog control it is very difficult to realize complex spread-spectrum clocking, however this paper shows that it is relatively easy to implement spread-spectrum EMI-reduction using digital control. The proposed algorithm was verified using a power converter simulator (SCAT).

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A signal detection system using noise statistical processing is proposed. By approaching the problems of low voltage and high noise from miniaturization of a device from a stochastic point of view, a faint-signal receiving system that can effectively detect subthreshold and noise level signals has been developed. In addition, an alternative to statistical processing is proposed, and would be successfully implemented on a circuit. For the proposed signal detection method, the detection sensitivity was investigated using numerical simulation, and the detection sensitivity was sufficiently high to detect even a signal with a signal-to-inherent-noise ratio of -14dB. Thus, it is anticipated that the application of this system to an integrated circuit will have a significant impact on signal processing.

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Sawtooth wave generator which has very steep down-slope and little amplitude and oscillation frequency error, is proposed. Because the down-slope is achieved by switching two triangular waves exclusively, the shape of the down-slope becomes very steep. The proposed method realizes not only the steep down-slope but also less amplitude error and less oscillation frequency error compared with conventional method. Spectre simulations are performed by using 0.18µm CMOS process and transient simulation results show the proposed circuit has quite less amplitude and frequency error for 5MHz oscillation compared with the conventional method.

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A novel voltage measurement circuit which utilizes process variation is proposed. Using the proposed circuit, the voltage of a nonperiodic waveform at a particular time point can be accurately captured by a single clock pulse (one-shot measurement). The proposed circuit can be designed without compensation circuits against process variation, and thus occupies only a small area. An analytical expression of offset voltage for the comparator utilizing process variation (UPV-comparator), which plays a key role in the proposed circuit, is derived and design considerations for the proposed circuit are discussed. The circuit operation is confirmed through SPICE simulation using 90nm CMOS device models. The -0.04 and -3dB bandwidths (99% and 50% amplitudes) of the proposed circuit are about 10MHz and far over 1GHz, respectively. The circuit area is also estimated using an experimental layout.

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Circuits utilizing advanced process technologies have to correctly account for device parameter variation to optimize its performance. In this paper, analytical formulas for evaluating path delay variation of Multi-Threshold CMOS (MTCMOS) circuits are proposed. The proposed formulas express path delay and its variation as functions of process parameters that are determined by fabrication technology (threshold voltage, carrier mobility, etc.) and the circuit parameters that are determined by circuit structure (equivalent load capacitance and the concurrently switching gates). Two procedures to obtain the circuit parameter sets necessary in the calculation of the proposed formulas are also defined. With the proposed formulas, calculation time of a path delay variation becomes three orders faster than that of Monte-Carlo simulation. The proposed formulas are suitably applied for efficient design of MTCMOS circuits considering process variation.

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In this paper, we propose a distance-based howling canceller with high speech quality. We have developed a distance-based howling canceller that uses only distance information by noticing the property that howling occurs according to the distance between a loudspeaker and a microphone. This method estimates the distance by transmitting a pilot signal from the loudspeaker to the microphone. Multiple frequency candidates for each howling are computed from the estimated distance and eliminated by cascading notch filters that have nulls at them. However degradation of speech quality occurs at the howling canceller output. The first cause is a shot noise occurrence at the beginning and end of the pilot signal transmission due to the discontinuous change of the amplitude. We thus develop a new pilot signal that is robust against ambient noises. We can then reduce the shot noise effect by taking the amplitude small. The second one is a speech degradation caused from overlapped stopbands of the notch filters. We thus derive a condition on the bandwidths so that stopbands do not overlap, and propose an adaptive bandwidth scheme which changes the bandwidth according to the distance.

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The recognition performance of the conventional 3D face recognition algorithm using ICP (Iterative Closest Point) is degraded for the 3D face data with expression changes. Addressing this problem, we consider the use of the expression-invariant local regions of a face. We find the expression-invariant regions through the distance analysis between 3D face data with the neutral expression and smile, and propose a robust 3D face recognition algorithm using passive stereo vision. We demonstrate efficient recognition performance of the proposed algorithm compared with the conventional ICP-based algorithm through the experiment using a stereo face image database which includes the face images with expression changes.

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This paper presents a framework of multimode fully digital receiver implementation using direct RF-to-digital conversion. In this architecture the entire band including multiple RF systems is directly converted to digital by a wideband high speed ADC, and the RF systems can be easily switched by only digital signal processing with the minimum analog RF components. The digital RF front-end consists of parallel processing blocks for parallel data streams considering practical ADC's configuration. The RF signals are converted into baseband through digital IF stage and the data rates are made down by two steps of decimation. In this paper, a principle investigation into a dualmode system implementation is presented for simplicity. The circuit resource and the robustness to the spurs (spurious outputs) of an NCO (numerically controlled oscillator) in the proposed design will be presented. The proposed architecture was implemented with an FPGA on the developed prototype system and the operations were also verified.

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H.264 is the latest HDTV video compression standard, which provides a significant improvement in coding efficiency at the cost of huge computation complexity. After transform and quantization, if all the coefficients of the block's residue data are zero, this block is called all-zero block (AZB). Provided that an AZB can be detected early, the process of transform and quantization on an AZB can be skipped, which reduces significant redundant computations. In this paper, a theoretical analysis is performed for the sufficient condition for AZB detection. As a result, a partial sum of absolute difference (SAD) based 4 × 4 AZB detection algorithm is derived. And then, a hardware-oriented AZB detection algorithm is proposed by modifying the order of SAD calculation. Furthermore, a quantization parameter (QP) oriented 8 × 8 AZB detection algorithm is proposed according to the AZB's statistical analysis. Experimental results show that the proposed algorithm outperforms the previous methods in all cases and achieves major improvement of computation reduction in the range from 6.7% to 42.3% for 4 × 4 blocks, from 0.24% to 79.48% for 8 × 8 blocks. The computation reduction increases as QP increases.

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Motion estimation (ME) is a computation and data intensive module in video coding system. The search window reuse methods play a critical role in bandwidth reduction by exploiting the data locality in video coding system. In this paper, a search window reuse method (Level C+) is proposed for MPEG-2 to H.264/AVC transcoding. The proposed method is designed for ultra-low bandwidth application, while the on-chip memory is not a main constraining factor. By loading search window for the motion estimation unit (MEU) and applying motion vector clipping processing, each MB in MEU can utilize both horizontal and vertical search reuse. A very low bandwidth level (R_α < 2) can be achieved with an acceptable on-chip memory.

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Three-dimensional integrated circuits (3-D ICs), i.e., stacked dies, can alleviate the interconnect problem coming with the decreasing feature size and increasing integration density, and promise a solution to heterogenous integration. The vertical connection, which is generally implemented by the through-the-silicon via, is a key technology for 3-D ICs. In this paper, given 3-D circuit placement or floorplan results with white space reserved between blocks for inter-layer interconnections, we proposed methods for assigning inter-layer signal via locations. Introducing a grid structure on the chip, the inter-layer via assignment of two-layer chips can be optimally solved by a convex-cost max-flow formulation with signal via congestion optimized. As for 3-D ICs with three or more layers, the inter-layer signal via assignment is modeled as an integral min-cost multi-commodity flow problem, which is solved by a heuristic method based on the lagrangian relaxation. Relaxing the capacity constraints in the grids, we transfer the min-cost multi-commodity flow problem to a sequence of lagrangian sub-problems, which are solved by finding a sequence of shortest paths. The complexity of solving a lagrangian sub-problem is $O(n_{nt}n_g^2)$, where n_nt is the number of nets and n_g is the number of grids on one chip layer. The experimental results demonstrated the effectiveness of the method.

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A scheduling algorithm aims to minimize the overall execution time of the program by properly allocating and arranging the execution order of the tasks on the core processors such that the precedence constraints among the tasks are preserved. In this paper, we present a new scheduling algorithm by using geometry analysis of the Task Precedence Graph (TPG) based on A^* search technique and uses a computationally efficient cost function for guiding the search with reduced complexity and pruning techniques to produce an optimal solution for the allocation/scheduling problem of a parallel application to parallel and multiprocessor architecture. The main goal of this work is to significantly reduce the search space and achieve the optimality or near optimal solution. We implemented the algorithm on general task graph problems that are processed on most of related search work and obtain the optimal scheduling with a small number of states. The proposed algorithm reduced the exhaustive search by at least 50% of search space. The viability and potential of the proposed algorithm is demonstrated by an illustrative example.

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For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold constraint, as well as the setup constraint, becomes critical for latching a correct signal under delay variations. This paper treats the hold constraint in a datapath circuit, and discusses a register assignment in high level synthesis considering delay variations. Our approach to ensure the hold constraint under delay variations is to enlarge the minimum-path delay between registers, which is called minimum-path delay compensation (MDC) in this paper. MDC can be done by inserting delay elements mainly in non-critical paths of a functional unit (FU). One of our contributions is to show that the minimization of the number of minimum-path delay compensated FUs is NP-hard in general, and it is in the class P if the number of FUs is a constant. A polynomial time algorithm for the latter is also shown in this paper. In addition, an integer linear programming (ILP) formulation is also presented. The proposed method generates a datapath having (1) robustness against delay variations, which is ensured partly by MDC technique and partly by SRV-based register assignment, and (2) the minimum possible numbers of MDCs and registers.

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In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily simultaneously, the circuit performance such as the clock period is expected to be improved by delay insertion. However, if the amount of inserted delays is too much, then the circuit is changed too much and the circuit performance might not be improved. In this paper, we propose an efficient delay insertion method that minimizes the amount of inserted delays in the clock period improvement in general-synchronous framework. In the proposed method, the amount of inserted delays is minimized by using an appropriate clock schedule and by inserting delays into appropriate places in the circuit. Experiments show that the proposed method can obtain optimum solutions in short time in many cases.

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A subdivision of a rectangle into rectangular faces with horizontal and vertical line segments is called a rectangular drawing or floorplan. It has been an open problem to determine whether there exist a polynomial time algorithm for computing R(n). We affirmatively solve the problem, that is, we introduce an O(n⁴)-time and O(n³)-space algorithm for R(n). The algorithm is based on a recurrence for R(n), which is the main result of the paper. We also implement our algorithm and computed R(n) for n ≤ 3000.

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Utilizing a heterogeneous multiprocessor system has become a popular design paradigm to build an embedded system at a cheap cost within short development time. A reliability issue for embedded systems, which is vulnerability to single event upsets (SEUs), has become a matter of concern as technology proceeds. This paper discusses reliability inherent in heterogeneous multiprocessors and proposes task scheduling for minimizing SEU vulnerability of them. This paper experimentally shows that increasing performance of a CPU core deteriorates its reliability. Based on the experimental observation, we propose task scheduling for reducing SEU vulnerability of a heterogeneous multiprocessor system. The experimental results demonstrate that our task scheduling technique can reduce much of SEU vulnerability under real-time constraints.

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This paper proposes an adaptive algorithm for identifying unknown systems containing nonlinear amplitude characteristics. Usually, the nonlinearity is so small as to be negligible. However, in low cost systems, such as acoustic echo canceller using a small loudspeaker, the nonlinearity deteriorates the performance of the identification. Several methods preventing the deterioration, polynomial or Volterra series approximations, have been hence proposed and studied. However, the conventional methods require high processing cost. In this paper, we propose a method approximating the nonlinear characteristics with a piecewise linear curve and show using computer simulations that the performance can be extremely improved. The proposed method can also reduce the processing cost to only about twice that of the linear adaptive filter system.

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A state-discretization approach [11], which was introduced for stability of constant delayed systems, will be extended to time-varying delayed systems. The states not only in constructing the Lyapunov-Krasovskii functional but also in designing the integral inequality technique [12] will be discretized. Based on the discretized-state, [9],[17]'s piecewise analysis method will be applied to confirm the system stability in whole delay bound. Numerical examples show that the results obtained by this criterion improve the allowable delay bounds over the existing results in the literature.

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This paper studies a simple spiking oscillator having piecewise constant vector field. Repeating vibrate-and-fire dynamics, the system exhibits various spike-trains and we pay special attention to chaotic spike-trains having line-like spectrum in distribution of inter-spike intervals. In the parameter space, existence regions of such phenomena can construct infinite window-like structures. The system has piecewise linear trajectory and we can give theoretical evidence for the phenomena. Presenting a simple test circuit, typical phenomena are confirmed experimentally.

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As we scale toward nanometer technologies, the increase in interconnect parameter variations will bring significant performance variability. New design methodologies will emerge to facilitate construction of reliable systems from unreliable nanometer scale components. Such methodologies require new performance models which accurately capture the manufacturing realities. In this paper, we present a Linear Fractional Transform (LFT) based model for interconnect parametric uncertainty. The new model formulates the interconnect parametric uncertainty as a repeated scalar uncertainty structure. With the help of generalized Balanced Truncation Realization (BTR) and Linear Matrix Inequalities (LMI's), the porposed model reduces the order of the original interconnect network while preserves the stability. The LFT based new model even guarantees passivity if the BTR reduction is based on solutions to a pair of Linear Matrix Inequalities (LMI's) generated from Lur'e equations. In case of large number of uncertain parameters, the new model may be applied successively: the uncertain parameters are partitioned into groups, and with regard to each group, LFT based model is applied in turns.

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Low energy and high performance embedded processor is crucial in the future nomadic embedded systems design. Improvement of memory accesses, especially improvement of spatial and temporal locality is well known technique to reduce energy and increase performance. However, after transformations that improve locality, address calculation often becomes a bottleneck. In this paper, we propose novel AGU (Address Generation Unit) exploration and mapping technique based on a reconfigurable AGU model. Experimental results show that the proposed techniques help exploring AGU architectures effectively and designers can get trade-offs of real life applications for about 10 hours.

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Sensor networks have promising applications such as battlefield surveillance, biological detection, and emergency navigation, etc. Crucial problems in sensor networks are energy-efficiency and collision avoidance in wireless communication. To deal with the problems, we consider a self-stabilizing solution to the construction of k disjoint sense-sleep trees, where range adjustment and the use of GPS are allowed. Each root is determined by its identifier and is distinguished by its color, the identification of a tree. Using a dominating k-partition rule, each non-root node first determines a color irrelevant to the root. Then, the non-root node determines a parent node that is equally colored with minimal distance. If there is no appropriate parent, the range is extended or shrunk until the nearest parent is determined. Finally, we perform a simulation.

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In this paper, a novel model of Gaussian pulse propagation in optical fiber is proposed to comprehensively analyze the impact of Group Velocity Dispersion (GVD) on the performance of two-dimensional wavelength hopping/time spreading optical code division multiple access (2-D WH/TS OCDMA) systems. In addition, many noise and interferences, including multiple access interference (MAI), optical beating interference (OBI), and receiver's noise are included in the analysis. Besides, we propose to use the heterodyne detection receiver so that the receiver's sensitivity can be improved. Analytical results show that, under the impact of GVD, the number of supportable users is extremely decreased and the maximum transmission length (i.e. the length at which BER ≤ 10^-9 can be maintained) is remarkably shortened in the case of normal single mode fiber (ITU-T G.652) is used. The main factor that limits the system performance is time skewing. In addition, we show how the impact of GVD is relieved by dispersion-shifted fiber (ITU-T G.653). For example, a system with 32 × 1Gbit/s users can achieve a maximum transmission length of 111km when transmitted optical power per bit is -5dBm.

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Halftoning is an important process to convert a gray scale image into a binary image with black and white pixels. The Direct Binary Search (DBS) is one of the well-known halftoning methods that can generate high quality binary images for middle tone of original gray scale images. However, binary images generated by the DBS have clippings, that is, have no tone in highlights and shadows of original gray scale images. The first contribution of this paper is to show the reason why the DBS generates binary images with clippings, to clarify the range of tone in original images that may have clipping, and to present a clipping-free DBS-based halftoning algorithm. The key idea is to apply the ordered dither using a threshold array generated by DBS-based method, to highlights and shadows, and then use the DBS. The second contribution is to extend the DBS to generate L-level multitone images with each pixel taking one of the intensity levels ${0\over L-1}$, ${1\over L-1}$, $\ldots$, ${L-1\over L-1}$. However, clippings appear in highlights, middle tone, and shadows of generated L-level multitone images. The third contribution of this paper is to modify the multitone version of the DBS to generate a clipping-free L-level multitone images. The resulting multitone images are so good that they reproduce the tones and the details of the original gray scale images very well.

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DVC based video codecs proposed in the literature generally include a reverse (feedback) channel between the encoder and the decoder. This channel is used to communicate the dynamic parity bit request messages from the decoder to the encoder resulting in an optimum dynamic variable rate control implementation. However it is observed that this dynamic feedback mechanism is a practical hindrance in a number of practical consumer electronics applications. In this paper we proposed a novel transform domain Unidirectional Distributed Video Codec (UDVC) without a feedback channel. First, all Wyner-Ziv frames are divided into rectangular macroblocks. A simple metric is used for each block to represent the correlations between the corresponding blocks in the adjacent key frame and the Wyner-Ziv frame. Based on the value of this metric, parity is allocated dynamically for each block. These parities are either stored for offline processing or transmitted to the DVC decoder for on line processing. Simulation results show that the proposed codec outperforms the existing UDVC solutions by a significant margin.

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The core of the support vector machine (SVM) problem is a quadratic programming problem with a linear constraint and bounded variables. This problem can be transformed into the second order cone programming (SOCP) problems. An interior-point-method (IPM) can be designed for the SOCP problems in terms of storage requirements as well as computational complexity if the kernel matrix has low-rank. If the kernel matrix is not a low-rank matrix, it can be approximated by a low-rank positive semi-definite matrix, which in turn will be fed into the optimizer. In this paper we present two SOCP formulations for each SVM classification and regression problem. There are several search direction methods for implementing SOCPs. Our main goal is to find a better search direction for implementing the SOCP formulations of the SVM problems. Two popular search direction methods: HKM and AHO are tested analytically for the SVM problems, and efficiently implemented. The computational costs of each iteration of the HKM and AHO search direction methods are shown to be the same for the SVM problems. Thus, the training time depends on the number of IPM iterations. Our experimental results show that the HKM method converges faster than the AHO method. We also compare our results with the method proposed in Fine and Scheinberg (2001) that also exploits the low-rank of the kernel matrix, the state-of-the-art SVM optimization softwares SVMTorch and SVM^light. The proposed methods are also compared with Joachims ‘Linear SVM’ method on linear kernel.

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It is essential, as bandwidths of wireless communications get wider, to evaluate the imbalances among quadrature mixer ports, in terms of carrier phase offset, IQ gain imbalance, and IQ skew. Because it is time consuming to separate skew, gain imbalance and carrier phase offset evaluation during test is often performed using a composite value, without separation of the imbalance factors. This paper describes an algorithm for enabling separation among quadrature mixer gain imbalance, carrier phase offset, and skew. Since the test time is reduced by the proposed method, it can be applied during high volume production testing.

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In many engineering problems it is required to convert a polynomial into another polynomial through a transformation. Due to its wide range of applications, the polynomial transformation has received much attention and many techniques have been developed to compute the coefficients of a transformed polynomial from those of an original polynomial. In this letter a new result is presented concerning the transformation matrix for arbitrary polynomial transformation. A simple algorithm is obtained which enables one to successively compute transformation matrices of various order.

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In this letter, we propose a new multi-step maximum likelihood predictor with a finite impulse response (FIR) structure for discrete-time state-space signal models. This predictor is called a maximum likelihood FIR predictor (MLFP). The MLFP is linear with the most recent finite outputs and does not require a prior initial state information on a receding horizon. It is shown that the proposed MLFP possesses the unbiasedness property and the deadbeat property. Simulation study illustrates that the proposed MLFP is more robust against uncertainties and faster in convergence than the conventional multi-step Kalman predictor.

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This primary objective of this study is to demonstrate simulation and ground-based experiment for the attitude control of flexible spacecraft. A typical spacecraft structure consists of the rigid body and flexible appendages which are large flexible solar panels, parabolic antennas built from light materials in order to reduce their weight. Therefore the attitude control has a big problem because these appendages induce structural vibration under the excitation of external forces. A single-axis rotational simulator with a flexible arm is constructed with on-off air thrusters and reaction wheel as actuation. The simulator is also equipped with payload pointing capability by simultaneous thruster and DC servo motor actuation. The experiment of flexible spacecraft attitude control is performed using only the reaction wheel. Using the reaction wheel the performance of the fuzzy-PID controller is illustrated by simulation and experimental results for a single-axis rotational simulator.

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This paper presents a deadbeat control scheme for linear systems with state constraints. The proposed controller increases the number of steps on-line for the deadbeat tracking performance, satisfying given admissible state constraints. LMI conditions are given to minimize the unavoidable step delay. The proposed schemes can be easily developed by using LMI approach, and are validated by numerical simulation.

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Due to the fast development of Internet and the related IT technologies, it becomes more and more easier to access a large amount of data. k-means clustering is a powerful and frequently used technique in data mining. Many research papers about privacy-preserving k-means clustering were published. In this paper, we analyze the existing privacy-preserving k-means clustering schemes based on the cryptographic techniques. We show those schemes will cause the privacy breach and cannot output the correct results due to the faults in the protocol construction. Furthermore, we analyze our proposal as an option to improve such problems but with intermediate information breach during the computation.

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