Substrate noise coupling has been seriously concerned in the design of advanced analog and radio frequency (RF) integrated circuits (ICs). This paper reviews recent advancements in the modeling, analysis, and evaluation of substrate noise coupling at IC chip level. Noise generation from digital circuits and propagation to the area of analog circuits are clearly visualized both by full-chip simulation as well as by on-chip measurements, for silicon test vehicles. The impacts of substrate noise coupling are also in-depth discussed at device, circuit, as well as system levels. Overall understanding of substrate noise coupling will then provide the basics for highly reliable design of analog and RF ICs.

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In this paper, the charge pump efficiency is discussed, and a dual charge pump circuit with complementary architecture using charge sharing clock scheme is presented. The proposed charge sharing clock generator is able to recover the charge from parasitic-capacitor charging and discharging, so that the dynamic power loss in the pumping process is reduced by a half. To preserve the overlapping period of the four-phase clock used for threshold cancellation technique, two complementary sets of clocks are generated from the proposed clock generator, and each set feeds a certain branch of the dual charge pump to achieve the between-branch charge sharing. A test chip is fabricated in 0.18µm process, and the area penalty of the proposed charge sharing clock generator is 1%. From the measurement results, the proposed charge pump shows an overall power efficiency increase with a peak value of 63.7% comparing to 52.3% of a conventional single charge pump without charge sharing, and the proposed clock scheme shows no degradation on the driving capability while the output ripple voltage is reduced by 43%.

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A technique to reduce noise transfer functions (NTF) of switched-capacitor (SC) integrators without changing their signal transfer functions (STF) is proposed. The proposed technique based on a simple reconnection scheme of multiple sampling capacitors. It can be implemented into any SC integrators as long as they have a transfer delay. A design strategy is also given to reduce the effect of parasitic capacitors. An SC integrator with a small total capacitance and a low noise transfer gain based on the proposed technique is also proposed. For a given design example, the total capacitance and the simulated noise transfer gain of the proposed SC integrator are 37% and 90% less than the conventional one.

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This paper analyzes a pseudo-differential dynamic comparator with a dynamic pre-amplifier. The transient gain of a dynamic pre-amplifier is derived and applied to equations of the thermal noise and the regeneration time of a comparator. This analysis enhances understanding of the roles of transistor's parameters in pre-amplifier's gain. Based on the calculated gain, two calibration methods are also analyzed. One is calibration of a load capacitance and the other is calibration of a bypass current. The analysis helps designers' estimation for the accuracy of calibration, dead-zone of a comparator with a calibration circuit, and the influence of PVT variation. The analyzed comparator uses 90-nm CMOS technology as an example and each estimation is compared with simulation results.

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This paper presents a low distortion 3rd-order continuous-time delta-sigma modulator for a worldwide digital TV-receiver whose peak SNDR is 69.8dB and SNR is 70.2dB under 1V power supply. To enhance SNDR performance, the mechanisms to occur harmonic distortions at feedback current-steering DAC and flash ADC have been analyzed. A low power tuning system using RC-relaxation oscillator has been developed in order to achieve high yield against PVT variations. A 3rd-order modulator with modified single opamp resonator contributes to cost reduction by realizing a very compact circuit. Reduction schemes of the distortions enabled the modulator to achieve FOM of 0.18pJ/conv-step.

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This paper presents an area-effective bandwidth enhancement technique using interwoven inductors. Inductive peaking is a common practice for bandwidth enhancement, however the area overhead of inductors is a serious issue. We implement six or four inductors into an interwoven inductor. Furthermore parasitics of the inductors can be reduced. The proposed inductor is applied to a laser-diode driver in a 0.18µm CMOS. Compared to conventional shunt-peaking, the proposed circuit achieves 1.6 times faster operation and 60% reduction in power consumption under the condition for the same amount of data transmission and the LD driving current. The interwoven inductor can reduce the circuit area by 26%. Parasitic capacitance in interwoven inductor is discussed. Simulation results reveal that line-to-line capacitance is a significant factor on bandwidth degradation.

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In this paper, a CMOS Class-G supply modulation for polar power amplifiers with high average efficiency and low ripple noise is proposed. In the proposed Class-G supply modulation, the parallel supply modulations which are controlled by switch signals are utilized for low power and high power supplies to increase the average efficiency. A low dropout (LDO) is utilized to suppress the delta-modulated noise and provide a low ripple noise power supply. The proposed supply modulation has high efficiency at large output current as the conventional supply modulation, and it also has high efficiency and low ripple noise at the low output current. To verify the effectiveness of the proposed supply modulation, the proposed supply modulation was designed with 0.13µm CMOS process. The simulation results show that the proposed supply modulation achieves a maximum efficiency of 85.1%. It achieves an average efficiency of 29.3% and a 7.1% improvement compared with the conventional supply modulations with Class-E power amplifier. The proposed supply modulation also shows an excellent spurious free dynamic range (SFDR) of -73dBc for output envelope signal.

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At mm-wave frequency, the layout of CMOS transistors has a larger effect on the device performance than ever before in low frequency. In this work, the distance between the gate and drain contact (D_gd) has been enlarged to obtain a better maximum available gain (MAG). By using the asymmetric-layout transistor, a 0.6dB MAG improvement is realized when D_gd changes from 60nm to 200nm. A four-stage common-source low noise amplifier is implemented in a 65nm CMOS process. A measured peak power gain of 24dB is achieved with a power dissipation of 30mW from a 1.2-V power supply. An 18dB variable gain is also realized by adjusting the bias voltage. The measured 3-dB bandwidth is about 17GHz from 51GHz to 68GHz, and noise figure (NF) is from 4.0dB to 7.6dB.

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This paper proposes a dual-conduction class-C VCO for ultra-low supply voltages. Two cross-coupled NMOS pairs with different bias points are employed. These NMOS pairs realize an impulse-like current waveform to improve the phase noise in the low supply conditions. The proposed VCO was implemented in a standard 0.18µm CMOS technology, which oscillates at a carrier frequency of 4.5GHz with a 0.2-V supply voltage. The measured phase noise is -104dBc/Hz@1MHz-offset with a power consumption of 114µW, and the FoM is -187dBc/Hz.

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This paper proposes a diversity scheme for Multi-Input Multi-Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM) based on Radio Frequency (RF) signal processing. Although a 2×2 MIMO-OFDM system can double the capacity without expanding the occupied frequency bandwidth, we cannot get additional diversity gain using the linear MIMO decomposition method. The proposed method improves the bit error rate (BER) performance by making efficient use of RF signal processing. Computer simulation results show that the proposed scheme gives additional diversity gain.

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This paper considers the discrete model of the cart-pendulum system modeled by discrete mechanics, which is known as a good discretizing method for mechanical systems and has not been really applied to control theory. We first sum up basic concepts on discrete mechanics and discuss the explicitness of the linear approximation of the discrete Euler-Lagrange Equations. Next, the discrete cart-pendulum system is derived and analyzed from the viewpoint of solvability of implicit nonlinear control systems. We then show a control algorithm to stabilize the discrete cart-pendulum based on the discrete-time optimal regulator theory. Finally, some simulations are shown to demonstrate the effectiveness of the proposed algorithm.

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In this paper, we consider a stabilization problem for the cart-pendulum system based on discrete mechanics, which is known as a good discretizing method for mechanical systems and has not been really applied to control theory. First, the continuous and discrete cart-pendulum systems are explained. We next propose a transformation method that converts a discrete-time input derived from the discrete-time optimal regulator theory into a continuous-time zero-order hold input, and carry out some simulations on stabilization of the cart-pendulum system by the transformation method. Then, we apply not only our proposed method but also existing methods to an experimental laboratory of the cart-pendulum system and perform some experiments in order to verify the availability of the proposed method.

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In this paper, a new Hammerstein predistorter modeling for power amplifier (PA) linearization is proposed. The key feature of the model is that the cubic splines, instead of conventional high-order polynomials, are utilized as the static nonlinearities due to the fact that the splines are able to represent hard nonlinearities accurately and circumvent the numerical instability problem simultaneously. Furthermore, according to the amplifier's AM/AM and AM/PM characteristics, real-valued cubic spline functions are utilized to compensate the nonlinear distortion of the amplifier and the following finite impulse response (FIR) filters are utilized to eliminate the memory effects of the amplifier. In addition, the identification algorithm of the Hammerstein predistorter is discussed. The predistorter is implemented on the indirect learning architecture, and the separable nonlinear least squares (SNLS) Levenberg-Marquardt algorithm is adopted for the sake that the separation method reduces the dimension of the nonlinear search space and thus greatly simplifies the identification procedure. However, the convergence performance of the iterative SNLS algorithm is sensitive to the initial estimation. Therefore an effective normalization strategy is presented to solve this problem. Simulation experiments were carried out on a single-carrier WCDMA signal. Results show that compared to the conventional polynomial predistorters, the proposed Hammerstein predistorter has a higher linearization performance when the PA is near saturation and has a comparable linearization performance when the PA is mildly nonlinear. Furthermore, the proposed predistorter is numerically more stable in all input back-off cases. The results also demonstrate the validity of the convergence scheme.

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We present area- and power-efficient pipeline 128- and 128/64-point fast Fourier transform (FFT) processors for 8x8 multiple-input multiple-output orthogonal frequency multiplexing (MIMO-OFDM) systems based on the specification framework of IEEE 802.11ac WLANs. Our new FFT processors use mixed-radix multipath delay commutator (MRMDC) architecture from the point of view of low complexity and high memory use. A conventional MRMDC architecture induces large circuits in delay commutators, which change the order of data sequences for the butterfly units. The proposed architecture replaces delay elements with new commutators that cooperate with other MIMO-OFDM processing blocks. These commutators are inserted in the front and rear of the input and output memory units. Our FFT processors exhibit a 50-51% reduction in logic gates and 70-72% reduction in power dissipation as compared with conventional ones.

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In deep-submicron era, wire delay is becoming a bottleneck while pursuing higher system clock speed. Several distributed register (DR) architectures are proposed to cope with this problem by keeping most wires local. In this article, we propose the distributed register-file microarchitecture with inter-island delay (DRFM-IID). Though DRFM-IID is also one of the DR-based architectures, it is considered more practical than the previously proposed DRFM, in terms of delay model. With such delay consideration, the synthesis task is inherently more complicated than the one without inter-island delay concern since uncertain interconnect latency is very likely to seriously impact on the whole system performance. Therefore we also develop a performance-driven architectural synthesis framework targeting DRFM-IID. Several factors for evaluating the quality of results, such as number of inter-island transfers, timing-criticality of transfer, and resource utilization balancing, are adopted as the guidance while performing architectural synthesis for better optimization outcomes. The experimental results show that the latency and the number of inter-cluster transfers can be reduced by 26.9% and 37.5% on average; and the latter is commonly regarded as an indicator for power consumption of on-chip communication.

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We implement one-out-of-two bit oblivious transfer (OT) based on the assumptions used in the McEliece cryptosystem: the hardness of decoding random binary linear codes, and the difficulty of distinguishing a permuted generating matrix of Goppa codes from a random matrix. To our knowledge this is the first OT reduction to these problems only. We present two different constructions for oblivious transfer, one based on cut-and-chose arguments and another one which is based on a novel generalization of Bennett-Rudich commitments which may be of independent interest. Finally, we also present a variant of our protocol which is based on the Niederreiter cryptosystem.

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We propose a motion detection model, which is suitable for higher speed operation than the video rate, inspired by the neuronal propagation in the hippocampus in the brain. The model detects motion of edges, which are extracted from monocular image sequences, on specified 2D maps without image matching. We introduce gating units into a CA3-CA1 model, where CA3 and CA1 are the names of hippocampal regions. We use the function of gating units to reduce mismatching for applying our model in complicated situations. We also propose a map-division method to achieve accurate detection. We have evaluated the performance of the proposed model by using artificial and real image sequences. The results show that the proposed model can run up to 1.0ms/frame if using a resolution of 64 × 60 units division of 320 × 240 pixels image. The detection rate of moving edges is achieved about 99% under a complicated situation. We have also verified that the proposed model can achieve accurate detection of approaching objects at high frame rate (> 100fps), which is better than conventional models, provided we can obtain accurate positions of image features and filter out the origins of false positive results in the post-processing.

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We propose a structure-generalized blind spatial subtraction array (BSSA), and the theoretical analysis of the amounts of musical noise and speech distortion. The structure of BSSA should be selected according to the application, i.e., a channelwise BSSA is recommended for listening but a conventional BSSA is suitable for speech recognition.

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In this paper, we introduce a generalized minimum mean-square error short-time spectral amplitude estimator with a new prior estimation of the speech probability density function based on moment-cumulant transformation. From the objective and subjective evaluation experiments, we show the improved noise reduction performance of the proposed method.

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This letter focuses on the design of selective receivers for homogeneous scenarios where a very small number of secondary data are available. To this end, at the design stage it is assumed that the cell under test (CUT) contains a fictitious signal orthogonal to the nominal steering vector under the null hypothesis; the clutter covariance matrix is modeled as a random matrix with an inverse complex Wishart distribution. Under the above assumptions, we devise two Bayesian detectors based on the GLRT criterion, both one-step and two-step. It is shown that the proposed detectors have the same detection structure as their non-Bayesian counterparts, substituting the colored diagonal sample covariance matrix (SCM) for the classic one. Finally, a performance assessment, conducted by Monte Carlo simulations, has shown that our detectors ensure better rejection capabilities of mismatched signals than the existing Bayesian detectors, at the price of a certain loss in terms of detection of matched signals.

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In this letter, an area-efficient architecture for the hardware implementation of the real-time prime factor Fourier transform (PFFT) is presented. In the proposed architecture, a prime length DFT module with the one-point-per-cycle (OPPC) property is implemented by the parallel distributed arithmetic (DA), and a cyclic convolution feature is exploited to simplify the structure of the DA cells. Based on the proposed architecture, a real-time 65-point PFFT processor is designed, and the synthesis results show that it saves over 8% gates compared to the existing real-time 64-point DFT designs.

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This paper examines the robust performance of a load torque observer for the position control of a surface-mounted permanent magnet synchronous motor (PMSM) under parameter uncertainties. The load torque observer has been widely employed to compensate for unknown slow-varying disturbances without explicit analysis on the robustness against parameter uncertainties. By using the singular perturbation theory this paper presents an analysis on the robust performance of the load torque observer based on the reduced-order estimator. As the observer poles are placed sufficiently left of the complex plane, the feedforward compensation with estimation can recover nominal system performance without parameter uncertainties and load torque disturbance. An example shows the performance of the load torque observer.

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A method for efficiently representing the state equation in a class of max-plus linear systems is proposed. We introduce a construct referred to as ‘cell’ in which the list of possible longest paths is stored. By imposing interval constraints on the system parameters, we can reduce the complexity of the state equation. The proposed method would be useful in scheduling applications for systems with adjustable system parameters.

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Phase structure of nonlinear dynamical system is governed by the vector field and decides the trajectories. Accordingly, the power spectra of trajectories include the structural field effect on the phase space. In this paper, we develop a method for analyzing phase structure using power spectra of trajectories and reconstitute a potential function in the system.

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We propose an adaptive coding algorithm for digital hologram transmission based on server-client interaction. A client can visualize various images of 3D objects from a digital hologram, which are reconstructed on different depth planes. The client's requests for reconstruction depths are sent to the server. The server adaptively encodes and transmits the same object image as the client's reconstructed image. When the client changes the reconstruction depth, only the prediction error of the new image is transmitted. Experimental results show that, in some cases, the proposed algorithm reduces more than half of the distortion at the same bitrate compared with the conventional coding technique.

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