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This technical note is a review of the contract research at Ritsumeikan University for the “Highly Integrated, Complex MEMS Production Technology Development” Project (“Fine MEMS” Project) sponsored by New Energy and Industrial Technology Development Organization (NEDO). Our research focuses on characterization of physical properties of nanoscale microelectronic materials and carbon nanotube (CNT) to elucidate new effects for potential applications in advanced micro/nano electromechanical devices, and consists of two main parts. The first part deals with experimental evaluation of mechanical, thermal, and electrical properties of tungsten silicide (WSi) and CNT thin films. We have clarified that the WSi film will be promising as a structural material for high-performance capacitive micro accelerometer. In the second part, piezoresistive effect of single crystal silicon nanostructures has been theoretically and experimentally investigated. The p-type ultra-thin silicon nanowire (SiNW), in particular <001> oriented SiNW, will be a good piezoresistor with a giant longitudinal piezoresistance coefficient. We have carried out the research in cooperation with Hitachi, Ltd. and National Institute of Advanced Industrial Science and Technology (AIST), and these cooperative relationships have greatly contributed to the advancement of the research and development. Achievements in the contract research are very promising and significant for mechanical sensing applications.

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This paper reports fundamental technologies, properties, and new experimental results of SBB (Smart Bumpless Bonding) to realize MEMS-IC vertical integration. Although conventional bonding technologies have had difficulties integrating MEMS and its processing circuit because of their rough bonding surfaces, fragile structures, and thermal restriction, SBB technology realized the vertical integration without thermal treatment, any adhesive materials including bumps, and chemical mechanical polishing.
The SBB technology bonds sealing parts for vacuum sealing and electrodes for electrical connection simultaneously as published in previous experimental study. The plasma CVD SiO₂ is utilized to realize vacuum sealing as sealing material. And Au projection studs are formed on each electrode and connected electrically between two wafers by compressive plastic deformation and surface activation. In this paper, new experimental results including vacuum sealing properties, electrical improvement, IC bonding results on the described fundamental concept and properties are reported.

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We have been developing the pseudo-SOC technology for one-chip module integration of heterogeneous devices that realizes high electrical performance and high density of devices embodying the advantages of both SOC technology and SIP technology. Especially, this technology is available for MEMS-LSI integration. We developed a 0.2mm-thickness one-chip module integrating a MEMS shock sensor and a sensing amplifier LSI by applying this technology. The MEMS shock sensor and the sensing amplifier LSI were connected by high-rigidity epoxy resin optimized the material constants to reduce the stress and the warpage resulting from resin shrinkage due to curing. Then the planar insulating layer and the redistributed conducting layer were formed on it for the global layer. The MEMS shock sensor was preformed to be modularized with a glass cap. Electrical contacts were achieved by bonding of Au bumps on the MEMS fixed electrodes and via holes filled with Ag paste of the glass cap. Functional performance was confirmed by obtaining signal corresponding to the reference signal of the pick-up sensor. Furthermore, stress analysis was performed using the FEM model simulation considering the resin shrinkage.

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Multi-wall carbon nanotubes (CNT) were successfully composited in gold electroplated film. Aggregation of CNT in electroplated film was observed using a surfactant, since electrolyte ion such as SO₃^2- surrounds the colloids and weakens coulomb repulsive force between colloids. Chemical modification of the CNT was effective to disperse in the electrolyte. The amount of the CNT in the electrolyte was estimated around 0.02wt%. The CNT co-deposited gold film (CNT-Au) has some excellent properties for radio frequency micro-electro-mechanical systems (RF-MEMS) switch, compared with Au and platinum containing Au film (AuPt). The hardness of the CNT-Au film is larger than the Au film, as almost same as the AuPt film. Meanwhile, the electrical resistivity of CNT-Au is much smaller than the AuPt film, as same as Au film. In tribology test, the CNT-Au film has superior property than the Au film The CNT-Au film was applied to the contact points of the RF-MEMS switch. In terms of high power handling capability, the CNT-Au contact is superior to the Au film contacts.

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Back-end-of-line (BEOL) MEMS processes for a compact, high-precision pressure sensor was developed. A CMOS-LSI-integrated capacitive pressure-sensor was fabricated with a chip size of 0.72 mm² using developed BEOL MEMS processes. Multi-sensor chip (with a size of 1.7 by 1.9 mm²) which consists of pressure sensor, temperature sensor and high-precision measurement circuits was also fabricated, and precise atmospheric pressure measurement (∼ 10 Pa) was demonstrated. As the sensitivity of pressure sensor can be easily changed by the size of its MEMS capacitors, the pressure sensor is thus suitable for various pressure-range applications.

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In this paper, a tunable VCSEL (Vertical Cavity Surface Emitting Laser) fabricated by high precision bonding of a half VCSEL chip and a Si chip with a concave mirror on a movable membrane is presented. A tuning range of 55nm, a wavelength modulation over 500kHz, a peak power of 3.5mW and a side mode suppression ratio of about 60dB, and the structure and the fabrication process of the MEMS-VCSEL have been presented. Tunable lasers with wide tuning range and fast wavelength modulation with continuous wavelength sweep are suitable for optical measurement applications, such as optical fiber sensing, gas sensors, and OCT (Optical Coherence Tomography).

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We propose a fabrication method of three-dimensional silicon slopes using RIE-lag. RIE-lag is a lag of an etching rate depending on square openings area of a mask. We measured relationship between area of square openings and etched depths. We confirmed that etched depths were defined as a function of the square openings. With this relationship, we designed a mask with various sizes of the squares for slope structures. Square openings of various sizes were patterned using EB lithography. Silicon was etched vertically with ICP-RIE (Inductive Coupled Plasma - Reactive Ion Etching). By RIE-lag, trenches with multiple depths depending on the area of the square openings were formed. Silicon surface was smoothed by SF₆ isotropic dry etching. As a result, by the combination of ICP-RIE anisotropic etching RIE-lag and SF₆ isotropic etching, we fabricated 57° silicon slopes of surface roughness 10 nm in plane and 35 nm in slope surface.

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We propose a method to fix the positioning error of transferred bare chips on a substrate after the Temperature-Controlled Transfer (TCT) that we have previously developed. This TCT method is important for large area integration of heterogeneous materials. In the TCT process, the bare chips on an adhesive sheet are transferred and electrically connected to the substrate via Low-Melting Point Solder (LMPS). We reflowed the LMPS and used the surface tension of the LMPS to self-align the bare chips in position on the substrate. We experimentally confirmed that the self-alignment works when contact pads on the bare chip and the substrate were overlapped. The positioning error after the self-alignment process was within 0-15 % of the contact pad size.

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The authors have developed pseudo-SoC technology to realize MEMS-LSI integrated micro-chip. The pseudo-SoC technology consists of three technologies which are wafer reconfiguration technology, inter-chip redistribution layer technology, and pseudo-SoC thinning technology. In the wafer reconfiguration technology, the filling of resin and surface step between heterogeneous chips were improved through the optimization of vacuum printing process and resin material. These improvements reduced the warpage of reconfiguration wafer, leading to achievement of the reconfiguration wafer with 5 inch in diameter. In the inter-chip redistribution layer technology, the interface adherence between planar layer and inter-chip redistribution layer was improved, leading to the inter-chip redistribution layer with 1μm/1μm in line/space on reconfiguration wafer. In the pseudo-SoC thinning technology, thin pseudo-SoC device with 100μm in thickness was achieved through developing mechanical backside grinding process technology. Furthermore, ultra-thin pseudo-SoC which integrated electrostatic MEMS light valve and PWM driver IC was prototyped through developing the ultra-thin MEMS encapsulation technology.

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