All issues
Predecessor
- IEEJ Transactions on Industry Applications
- IEEJ Transactions on Electronics, Information and Systems
- IEEJ Transactions on Power and Energy
- IEEJ Transactions on Fundamentals and Materials
- The Journal of The Institute of Electrical Engineers of Japan
- The transactions of the Institute of Electrical Engineers of Japan.C
- The transactions of the Institute of Electrical Engineers of Japan.B
- The transactions of the Institute of Electrical Engineers of Japan.A
- The Journal of the Institute of Electrical Engineers of Japan
Volume 122, Issue 8
Displaying 1-5 of 5 articles from this issue
- |<
- <
- 1
- >
- >|
Special Issue Paper
-
Yukihisa Yoshida, Munehito Kumagai, Jun-ichi Ichikawa, Jiwei Jiao, Kaz ...Article type: Others
Subject area: Others
2002 Volume 122 Issue 8 Pages 391-397
Published: 2002
Released on J-STAGE: March 28, 2003
JOURNAL FREE ACCESSFor devices with bonded silicon and glass structures fabricated by deep-RIE, it is important to avoid damage at the silicon backside and sidewall during through-wafer etching in order to ensure reliability of devices. The silicon backside damage is caused by charge accumulation at the glass surface. This paper reports the novel method to avoid the processing damage occurred in silicon structures of accelerometers by means of an electrically conducting layer patterned onto the glass and connected with the silicon. The positions of silicon damage in the structural layout were identified without destruction of samples by using transparent indium tin oxide (ITO) films as the electrically conducting layer. From the experiments, it was found that there exists silicon damage caused by charge accumulation at the silicon islands isolated by deep-RIE and we present important rules for mask layout when utilizing this method. Finally, the improved results of shock tests are briefly shown.View full abstractDownload PDF (2483K) -
Yoshihiko Hirai, Masato Okano, Hiroyuki Okuno, Hiroshi Toyota, Hisao K ...Article type: Others
Subject area: Others
2002 Volume 122 Issue 8 Pages 398-403
Published: 2002
Released on J-STAGE: March 28, 2003
JOURNAL FREE ACCESSFabrication of a fine diffractive optical element on a Si chip is demonstrated using imprint lithography. A chirped diffraction grating, which has modulated pitched pattern with curved cross section is fabricated by an electron beam lithography, where the exposure dose profile is automatically optimized by computer aided system. Using the resist pattern as an etching mask, anisotropic dry etching is performed to transfer the resist pattern profile to the Si chip. The etched Si substrate is used as a mold in the imprint lithography. The Si mold is pressed to a thin polymer (Poly methyl methacrylate) on a Si chip. After releasing the mold, a fine diffractive optical pattern is successfully transferred to the thin polymer. This method is exceedingly useful for fabrication of integrated diffractive optical elements with electric circuits on a Si chip.View full abstractDownload PDF (1660K) -
Yoshihiko Hirai, Nobuyuki Takagi, Satoshi Harada, Yoshio TanakaArticle type: Others
Subject area: Others
2002 Volume 122 Issue 8 Pages 404-408
Published: 2002
Released on J-STAGE: March 28, 2003
JOURNAL FREE ACCESSFine pattern fabrication on a polymer surface is expected to realize low cost micro/miniaturized total analysis system (μ-TAS), or diffractive optical elements (DOE). Line and space patterns are fabricated on an acrylic plate and a poly L-Lactic acid plate by imprint lithography using Si/SiO2 mold. The mold is pressed to the polymer plate beyond its glass transition temperature and released after cooling down. Fine pattern fabrication on the polymer surface is successfully demonstrated without expensive advanced lithographic tool and dry etching system. The minimum feature size of the imprinted pattern is 300nm and field size is 1 inch square. This fabrication method is expected to apply for micro/nano structures such as micro/nano channels of micro/miniaturized total analysis system or diffractive optical elements.View full abstractDownload PDF (1461K)
Paper
-
Takaaki Suzuki, Kazuyoshi Uchino, Tetsurou Yokoi, Yumen Rai, Hiroyuki ...Article type: Others
Subject area: Others
2002 Volume 122 Issue 8 Pages 409-414
Published: 2002
Released on J-STAGE: March 28, 2003
JOURNAL FREE ACCESSSi based multi-layered print circuit board is developed. The Si wafer, which has the same thermal coefficient as mounted chips, of 4 inch size was used and we have fabricated the electrical feed through by filling the metal into the small holes prepared by ICP etching. Moreover the wafers with through holes and trenches were aligned and bonded to make the stacked layer structure and we had tried the metal filling into the holes and trenches. The fabricated device was tested by insulation measurement. As a result, insulating layer of more than 1GΩ was obtained.View full abstractDownload PDF (1801K)
Special Issue Letter
-
Manabu Yasui, Kuniyuki Kakushima, Yasuo Hirabayashi, Makoto Mita, Hiro ...Article type: Others
Subject area: Others
2002 Volume 122 Issue 8 Pages 415-416
Published: 2002
Released on J-STAGE: March 28, 2003
JOURNAL FREE ACCESSThis paper deals with the new method that makes micro-holes with electrodeposition photoresist (EDPR) as a sacrificial layer. The EDPR was deposited on a silicon-mold made by ICP-RIE. Ni film was plated on a silicon-mold covered with EDPR. Etched through a gap between a silicon-mold and the Ni film, the Ni film came off from the silicon-mold. As a result, we could make Ni films that have micro hole of 20.9μm in diameter, and 56μm in depth on an experimental basis, and verified the silicon-mold that lateral faces of columns did not bare scratch marks.View full abstractDownload PDF (652K)
- |<
- <
- 1
- >
- >|